Abstract: There is provided a method for representing unvalues in an unvalue-unaware memory of a computer processing system. The method includes the step of selecting arbitrary bit combinations to represent the unvalues, upon startup of the system. Upon performing a read operation from the memory, a read value is interpreted as an unvalue, when the read value matches at least one of the bit combinations. Upon performing a write operation to the memory, a value-unvalue-collision exception is raised, when a valid value is written to the memory and the valid value matches at least one of the bit combinations.

Abstract: A server complex including at least one hit server with item cache, used to process read and write operations relating to cached items from clients, and at least one miss server, serving as a link to other servers (e.g., web servers, file system servers, and databases) for receiving requests relayed from the hit server(s) which relate to non-cached items and for responding to same. The hit server is a general-purpose, generic, component, which is independent of concrete applications and is basically responsible for the performance; while a miss server is a highly-customizable component, which is responsible for flexibility, and is application specific. The inventive architecture provides improved performance whereby a server complex achieves exceptionally high throughput rates for local services (i.e.

Abstract: A system and method for enabling applications to pin a set of pages in memory for a predetermined duration in time. An application submits a request for pinning its memory for certain duration. As a compensation the applications may offer other currently mapped pages for replacement. The request may also include number of pages and duration of time. The request is granted with the constraint policies which the application is to follow. Such constraint policies include number of pages and length of time the pages may remain pinned in memory. When compensation pages are offered, those pages are replaced in place of the pages which are granted the privileged of being pinned. The present invention also provides page coloring compensation by including a compensation pool from where a compensation page having the same color as the one picked for replacement may be selected. The compensation pages offered by the application which are not used for compensating are returned subsequently to the application.

Abstract: The memory device includes an auxiliary memory and a useful memory. Both memories are provided with a plurality of memory entries. The auxiliary memory is intended for storing regions of an address space therein. This includes a plurality of addresses with which the useful memory may be addressed. A write/read access to a useful memory entry is not possible if a status field associated with the useful memory entry signals a restricting status and the address with which the useful memory entry is addressed lies within at least one of the address space regions stored in the auxiliary memory. Efficient region-selective flushing of the useful memory is possible with this procedure.

Abstract: A cache system in accordance with the present invention consists of one or more cache components and a set of one or more consistency-replacement functions. A cache component caches one or more items in its one or more cache entries. Items that hit in the cache can result in corresponding cache entries being read or written. Any valid entry in a cache component includes status information reflecting whether the entry has been accessed and whether it has been modified, and is linked to a consistency-action matrix that, in correspondence with the entry's status information and access type (i.e. read or write), determines what consistency action has to be executed in conjunction with the current entry access. Consistency actions and the consistency-action matrix are the inventive mechanisms for implementing cache-coherency and cache-replacement policies. Any valid entry in a cache is linked to a consistency-replacement function that implements one or more consistency and/or replacement policies.

Abstract: The method serves to operate an address translation device for translating a virtual address of a virtual address space comprising a plurality of pages into a physical address of a physical address space comprising a plurality of pages, with the use of a translation lookaside buffer and a page table. The address translation is performed in the following manner: the translation lookaside buffer is indexed to an index by the routing code associated with the virtual address or by a mapping of the routing code associated with the virtual address, or it is indexed to an index by a mapping of the routing code associated with the virtual address and the first address portion of the virtual address. In case of a TLB hit, a page table parsing is executed using only the virtual address. The routing code used to index the TLB is not included in the page table parsing.

Abstract: The method is intended for the generation of a check word for a bit string to check the integrity and authenticity of the bit string, the bit string comprising at least one data set consisting of a plurality of data words, each having the same word length defined by a number of bits. Here, a random number is generated for each data word, the number having the same number of bits as the data words. Further, first and second operand pairs are generated, each consisting of a data word and a random number. The data word and the random number of each first operand pair are subjected to a first linking operation, while the data word and the random number of each second operand pair is subjected to a second linking operation. The results of all operations applied to the first and second operand pairs are linked, the result of this linking being the check word of this data set.

Abstract: A dynamic derivation mechanism is defined which enables limited permissions to be dynamically and flexibly derived for executables based upon their authenticated description. The dynamic derivation mechanism uses the authenticated description to determine the maximal permissions that individual principals can delegate to the content. A principal's maximal permissions for content define a superset of the rights that that principal will actually delegate to that content. Although the maximal permissions are derived from predefined specifications, the specifications can be sensitive to runtime state on the downloader's system or previous delegations to enable the dynamic (i.e., runtime) derivation. Multiple principals can delegate a subset of their maximal permissions for the executable content. The mechanism uses policy for combining the delegated permissions into the content's runtime permissions.

Abstract: A cache system in accordance with the present invention consists of one or more cache components and a set of one or more consistency-replacement functions. A cache component caches one or more items in its one or more cache entries. Items that hit in the cache can result in corresponding cache entries being read or written. Any valid entry in a cache component includes status information reflecting whether the entry has been accessed and whether it has been modified, and is linked to a consistency-action matrix that, in correspondence with the entry's status information and access type (i.e. read or write), determines what consistency action has to be executed in conjunction with the current entry access. consistency actions and the consistency-action matrix are the inventive mechanisms for implementing cache-coherency and cache-replacement policies. Any valid entry in a cache is linked to a consistency-replacement function that implements one or more consistency and/or replacement policies.

Abstract: The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and secondary group information. If the tag of the cache entry addressed according to the above standard by indexing of the cache memory corresponds to the physical address, indexing is carried out again using the second group information associated with the physical address (and using the cache index of the virtual address). If the tag of the cache entry thus addressed still does not correspond to the physical address, a cache miss is signaled.

Abstract: In a virtually addressed and physically indexed cache memory, the allocation of a color of a cache entry can be changed for a color allocation of the virtual and physical pages by assigning a color information to each cache entry, by which a second cache address operation is executed after an unsuccessful first cache address operation. Should there still be no cache hit, another cache addressing is attempted by means of a color correction, i.e. an indexing of the cache memory using, among others, the physical color. Should this cache address operation also fail to produce a cache hit, there is a cache miss.