Abstract: A piston for an internal combustion engine having an upper part joined by a positive material connection to a lower part, wherein the lower part includes a skirt and at least one pin bore, wherein the upper part includes a combustion bowl and a piston crown with a crown edge, wherein at least one joining point is located in the area of a ring belt and/or in an outer wall of the combustion bowl. A method for producing a piston for internal combustion engines is disclosed.

Abstract: The invention relates to a piston in particular for an internal combustion engine, having a piston lower part, an upper part, an internal cooling channel having at least one coolant inlet opening and at least one outlet opening defined by a rim hole. The rim hole having a screw thread into which at least one tubular element is inserted and selectively positioned relative to the cooling channel for regulating the coolant level in a cooling channel.

Abstract: A method of determining an initial pressure prevailing between a master brake cylinder and an inlet valve of a wheel brake cylinder of a motor vehicle determines the initial pressure taking into consideration the variation of a voltage of a PWMoperated motor of a pump, which is used for the return delivery of brake fluid from a low-pressure accumulator into the master brake cylinder. Several characteristic quantities of the voltage variation are measured and converted to respective initial pressure values. The characteristic quantities or the initial pressure values determined therefrom are filtered or conditioned in the event of lack in quality or reliability of the measured characteristic quantities. The respective initial pressure values of similar size are averaged, and the averaged initial pressure values are temporally averaged in order to dampen fluctuations.

Abstract: The invention relates to an illuminating device for microscopes, wherein the light source has, in particular, a white light illumination having total daylight spectrum and/or an excitation light source for fluorescent colors. The inventive illuminating device for a microscope consists of surface or spatially arranged light sources, which are connected to a control unit for generating any desired illuminating patterns and illuminating spectrums, and an illuminating optic to image these illuminating patterns on the object to be examined. The light sources consist of LEDs (11) which excite at least one luminescence color (14) which is adapted to the wavelength which is emitted by the LEDs (11). The LEDs (11) are arranged concentrically to the optical axis of the illuminating device, preferably, in or in the vicinity of the aperture diaphragm plane.

Abstract: A method of determining an initial pressure which prevails between a master brake cylinder and an inlet valve of a wheel brake cylinder of a motor vehicle brake system. It determines the initial pressure taking into consideration the variation of a follow-up voltage of a clock-operated motor of a pump, which is used for the return delivery of brake fluid from a low-pressure accumulator into the master brake cylinder. Several characteristic quantities of the voltage variation are measured and in each case taken into account to determine an initial pressure value, and the quality and/or reliability of the measured characteristic quantities is evaluated. The characteristic quantities and/or the initial pressure values determined therefrom are filtered and/or conditioned in the event of lack in quality and/or reliability of the measured characteristic quanitites.

Abstract: A fixing device for fixing cameras and other optical devices to stands or for connecting them to other accessories, includes an adapter journal joined to the camera or other optical devices and a receiving device connected to the stand or other accessories and which is provided with an opening for receiving the adapter journal, and a rotatable locking device. The opening is configured as an insert opening on a part which can be displaced axially in an outward manner by means of housing part of the receiving device such that the adapter journal can be inserted radially into the insert opening.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present for an isolation element, a one-time operation on the isolation element is begun.

Abstract: A portable data storage configuration has a card base and a display device, the display device being fixed to the card base. The display device is only partially connected to the card base by the fixed connection. This mounting technique results in that almost no lateral or shear forces act on the display device.

Abstract: The present invention relates to conjugates of synthetic binding units and nucleic acids. The present invention also relates to methods for sorting and immobilizing nucleic acids on support materials using such conjugates by specific molecular addressing of the nucleic acids mediated by the synthetic binding systems. Particularly, the present invention also relates to novel methods of utilizing conjugates of synthetic binding units and nucleic acids to in active electronic array systems to produce novel array constructs from the conjugates, and the use of such constructs in various nucleic acid assay formats. In addition, the present invention relates to various novel forms of such conjugates, improved methods of making solid phase synthesized conjugates, and improved methods of conjugating pre-synthesized synthetic binding units and nucleic acids.

Abstract: A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites the electrical functions for the operation of the smart card. The system component terminates approximately evenly with the top side of the card body of the smart card. At least one of the electrical components is accessible from the top side of the smart card.

Abstract: A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: The invention relates to a telescopically extendible focusing hood which improves the viewing of the LCD screen of a digital camera in bright surrounding light. Said focusing hood can be fixed to the rear wall of the camera, surrounding the LCD screen. The focusing hood preferably has an anti-reflection-coated enlarging lens or glass disk which covers the entire cross-section of the focusing hood in the fixing plane. In its extended state, the focusing hood can be used with a single lens in the manner of a 35 mm camera finder. When the enlarging lens is pushed in, the focusing hood can be used with two lenses for assessing the image.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connecti

Abstract: An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.