Abstract: A thin film deposition system and method for forming photovoltaic cells, the system including a first deposition module including a titanium sputtering target and configured to deposit a titanium precursor layer of a diffusion barrier on the substrate, as the substrate moves through the first deposition module; a second deposition module configured to deposit a first electrode onto the diffusion barrier, as the substrate moves through the second deposition module; and a first connection unit configured to nitride at least a portion of the titanium precursor layer of the diffusion barrier, while the substrate moves though the first connection unit from the first deposition module to the second deposition module.

Abstract: A method of manufacturing a solar cell including depositing a first electrode over a substrate under vacuum, depositing at least one p-type semiconductor absorber layer over the first electrode without breaking the vacuum, where the p-type semiconductor absorber layer comprises a copper indium selenide (CIS) based alloy material, sputter depositing an n-type semiconductor layer over the at least one p-type semiconductor absorber layer to form zinc oxysulfide in the n-type semiconductor layer without breaking the vacuum, and depositing a second electrode over the n-type semiconductor layer without breaking the vacuum.

Abstract: A photovoltaic device interconnect contains a first connection region, a second connection region, and an overlap region disposed between the first and second connection regions. The interconnect includes a first dielectric layer disposed in the first connection region and the overlap region, a second dielectric layer disposed in the second connection region and overlapped with the first dielectric layer in the overlap region, an electrically conductive element including a wire or a metal foil, disposed on an upper surface of the first dielectric layer, and an electrically conductive network of nanowires disposed on a lower surface of the second dielectric layer and electrically connected to the conductive element in the overlap region.

Abstract: A photovoltaic device interconnect contains a first connection region, a second connection region, and an overlap region disposed between the first and second connection regions. The interconnect includes an electrically conductive layer disposed in the first, second, and overlap regions. The conductive layer includes an electrically conductive network of nanowires. A first dielectric layer is disposed on a lower surface of the conductive layer in the first connection region and the overlap region, and a second dielectric layer is disposed on an upper surface of the conductive layer in the second connection region and the overlap region.

Abstract: A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.

Abstract: A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.

Abstract: A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.

Abstract: A photovoltaic cell includes a p-type copper-indium-gallium-selenide absorber layer, where a content of Cu, In, and Ga in a first portion of the p-type copper-indium-gallium-selenide absorber layer satisfies the equation Cu/(In+Ga)?0.3, and where the content is measured in atomic percent.

Abstract: A photovoltaic device including a substrate, a first electrode layer over the substrate and a resistive p-type semiconductor layer over the first electrode layer. The device also includes a p-type absorber layer over the resistive p-type semiconductor layer, an n-type semiconductor layer over the p-type absorber layer and a second electrode layer over the n-type semiconductor layer. Additionally, a resistivity of the resistive p-type semiconductor layer is greater than a resistivity of the p-type absorber layer.