Abstract: A method for producing a wafer connection between a first and a second wafer. The method includes providing a first and second material for forming a eutectic alloy, providing a first wafer having a receiving structure for a die structure, filling the receiving structure with the first material, providing a second wafer having a die structure, the second material being situated on the die structure, providing a stop structure on the first and/or second wafer, so that when the two wafers are joined, a defined stop is provided, heating the first and second material at least to the eutectic temperature of the eutectic alloy, joining the first and second wafer so that the die structure is at least partly introduced into the receiving structure, the stop structure, the receiving structure, the die structure.

Abstract: A microelectronics device, in particular a thin-film electronics device, having at least one bearer substrate and having at least one pyramidally layered, piezo stack situated on the bearer substrate, which stack has at least one piezo element and at least one electrode, in particular a floor electrode, and having at least one contact opening situated on the at least one electrode. The microelectronics device has a diffusion blocking element that is situated on the at least one electrode at least partly at a distance from the piezo element, and/or the contact opening forms a contact surface that is at most as large as one one-thousandth of a surface of the at least one piezo element, and/or a length of an electrical path from the at least one contact opening to the at least one piezo element corresponds to at least twice the circumference of the at least one contact opening.

Abstract: A micromechanical device, in particular a micromirror device. The device has at least one first micromechanical component and one second micromechanical component. The first component and the second component are directly or indirectly joined to one another. The first micromechanical component has a first sub-body and at least one second sub-body. The first sub-body extends in a first plane and the second sub-body in a second plane different from the first plane. The first plane and the second plane extend parallel to one another and the first plane extends above the second plane. The second sub-body is arranged in a transitional region to the second micromechanical component. A second extent of the second sub-body in the longitudinal direction is greater than a first extent of the first sub-body in the longitudinal direction.

Abstract: A method for producing a microelectronic device, in particular a MEMS chip device, comprising at least one carrier substrate. At least one electrodynamic actuator made of a metal conductor formed at least largely of copper is applied to the carrier substrate in at least one method step. At least one piezoelectric actuator is applied to the carrier substrate in at least one further method step.

Abstract: A semiconductor component that includes at least one dielectric layer and at least one first electrode and one second electrode. A first defect type and a second defect type, which is different from the first defect type, are also present in dielectric layer. The at least two different defect types accumulate at one of the two electrodes as a function of a main operating voltage applied between the first electrode and the second electrode, and of a main operating temperature that is present at characteristic times ?1 and ?2, and generate the maximum changes in barrier height ??1 and ??2 at the electrodes. ?1 and ??1 are associated with the first defect type, and ?2 and ??2 are associated with the second defect type. ?1<?2 and ??1<??2 apply.

Abstract: A semiconductor component that includes at least one dielectric layer and at least one first electrode and one second electrode. In addition, at least two defect types different from one another are present in the dielectric layer. These at least two defect types different from one another move along localized defect states, each at an average effective distance, in the direction of one of the two electrodes as a function of an operating voltage that is applied between the first electrode and the second electrode, and an operating temperature that is present. The average effective distance is greater than 3.2 nm.

Abstract: A microelectronics device, in particular a thin-film electronics device, having at least one bearer substrate and having at least one pyramidally layered, piezo stack situated on the bearer substrate, which stack has at least one piezo element and at least one electrode, in particular a floor electrode, and having at least one contact opening situated on the at least one electrode. The microelectronics device has a diffusion blocking element that is situated on the at least one electrode at least partly at a distance from the piezo element, and/or the contact opening forms a contact surface that is at most as large as one one-thousandth of a surface of the at least one piezo element, and/or a length of an electrical path from the at least one contact opening to the at least one piezo element corresponds to at least twice the circumference of the at least one contact opening.

Abstract: A method for producing a wafer connection between a first and a second wafer. The method includes providing a first and second material for forming a eutectic alloy, providing a first wafer having a receiving structure for a die structure, filling the receiving structure with the first material, providing a second wafer having a die structure, the second material being situated on the die structure, providing a stop structure on the first and/or second wafer, so that when the two wafers are joined, a defined stop is provided, heating the first and second material at least to the eutectic temperature of the eutectic alloy, joining the first and second wafer so that the die structure is at least partly introduced into the receiving structure, the stop structure, the receiving structure, the die structure.

Abstract: A MEMS element is provided. The MEMS element includes: a substrate; a first passivation layer arranged on the substrate; a metal layer arranged on the first passivation layer; a second passivation layer arranged on the metal layer and on the first passivation layer; and a punch element, an electrically conductive diffusion-blocking layer being arranged on the punch element and on the second passivation layer, a first bonding element being arranged on the punch element.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: A production method for a wafer equipped with transparent plates includes: formation of a row of through-holes in a wafer; formation of at least one strip-shaped recess in a wafer surface, each of the through-holes of the same row intersecting partly with the respectively associated strip-shaped recess; an uninterrupted groove being formed in each intermediate region between two adjacent through-holes of the same row, the floor surface of the groove being oriented so as to be inclined relative to the wafer surface by an angle of inclination greater than 0° and less than 90°; and covering at least one through-hole with at least one transparent plate made of at least one material transparent to at least a sub-spectrum of electromagnetic radiation.

Abstract: A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Abstract: A manufacturing method is provided for a piezoelectric layer arrangement and a corresponding piezoelectric layer arrangement. The manufacturing method includes the steps: depositing a first electrode layer on a substrate; depositing a first insulating layer on the first electrode layer; forming a through opening in the first insulating layer to expose the first electrode layer within the through opening; depositing a piezoelectric layer on the first insulating layer and on the first electrode layer within the through opening; back-polishing the resulting structure to form a planar surface, on which a piezoelectric layer area, surrounded by the first insulating layer, is exposed; and depositing and structuring a second electrode layer on the first insulating layer, which contacts the piezoelectric layer area.

Abstract: A manufacturing method is provided for a piezoelectric layer arrangement and a corresponding piezoelectric layer arrangement. The manufacturing method includes the steps: depositing a first electrode layer on a substrate; depositing a first insulating layer on the first electrode layer; forming a through opening in the first insulating layer to expose the first electrode layer within the through opening; depositing a piezoelectric layer on the first insulating layer and on the first electrode layer within the through opening; back-polishing the resulting structure to form a planar surface, on which a piezoelectric layer area, surrounded by the first insulating layer, is exposed; and depositing and structuring a second electrode layer on the first insulating layer, which contacts the piezoelectric layer area.

Abstract: A production method for a wafer equipped with transparent plates includes: formation of a row of through-holes in a wafer; formation of at least one strip-shaped recess in a wafer surface, each of the through-holes of the same row intersecting partly with the respectively associated strip-shaped recess; an uninterrupted groove being formed in each intermediate region between two adjacent through-holes of the same row, the floor surface of the groove being oriented so as to be inclined relative to the wafer surface by an angle of inclination greater than 0° and less than 90°; and covering at least one through-hole with at least one transparent plate made of at least one material transparent to at least a sub-spectrum of electromagnetic radiation.