Patents by Inventor Jock BOVINGTON
Jock BOVINGTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10826272Abstract: An optical source may include an optical gain chip that provides an optical signal and that is optically coupled to an SOI chip. The optical gain chip may include a reflective layer. Moreover, the SOI chip may include: a first optical waveguide, a first ring resonator that selectively optically coupled to a second optical waveguide and that performs phase modulation and filtering of the optical signal, the second optical waveguide, an amplitude modulator, and an output port. Note that the reflective layer in the optical gain chip and the amplitude modulator may define an optical cavity. Furthermore, a resonance of the first ring resonator may be aligned with a lasing wavelength, and the resonance of the first ring resonator and a resonance of the amplitude modulator may be offset from each other. Additionally, modulation of the first ring resonator and the amplitude modulator may be in-phase with each other.Type: GrantFiled: July 18, 2018Date of Patent: November 3, 2020Assignee: Axalume, Inc.Inventors: Jock Bovington, Xuezhe Zheng, Saman Saeedi, Ashok V. Krishnamoorthy
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Patent number: 10714895Abstract: An optical source may include an optical gain chip that provides an optical signal and that is optically coupled to an SOI chip. The optical gain chip may include a reflective layer. Moreover, the SOI chip may include: a common optical waveguide, a splitter that splits the optical signal into optical signals, a first pair of resonators that are selectively optically coupled to the common optical waveguide and that are configured to perform modulation and filtering of the optical signals, and a first bus optical waveguide that is selectively optically coupled to the first pair of resonators. Furthermore, resonance wavelengths of the resonators may be offset from each other with a (e.g., fixed) separation approximately equal or corresponding to a modulation amplitude, and a reflectivity of the first pair of resonators may be approximately independent of the modulation.Type: GrantFiled: July 18, 2018Date of Patent: July 14, 2020Assignee: Axalume, Inc.Inventors: Ashok V. Krishnamoorthy, Jock Bovington, Xuezhe Zheng, Saman Saeedi
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Patent number: 10365432Abstract: An integrated circuit that reduces back reflection of an optical signal is described. This integrated circuit may convey an optical signal in an optical waveguide defined in a layer in the integrated circuit. The integrated circuit may split the optical signal into portions of the optical signal using an optical splitter, and may convey the portions of the optical signal in at least two arms of the optical waveguide. Then, the integrated circuit may establish a predefined phase offset between the portions of the optical signal using at least a phase-offset device in one of the two arms. Furthermore, the integrated circuit may optically couple the portions of the optical signal at optical coupling interfaces at ends of the two arms. Note that the predefined phase offset may reduce the back reflection of the optical signal at the optical splitter to less than a threshold value.Type: GrantFiled: April 21, 2018Date of Patent: July 30, 2019Assignee: Axalume, Inc.Inventor: Jock Bovington
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Publication number: 20190027898Abstract: An optical source may include an optical gain chip that provides an optical signal and that is optically coupled to an SOI chip. The optical gain chip may include a reflective layer. Moreover, the SOI chip may include: a first optical waveguide, a first ring resonator that selectively optically coupled to a second optical waveguide and that performs phase modulation and filtering of the optical signal, the second optical waveguide, an amplitude modulator, and an output port. Note that the reflective layer in the optical gain chip and the amplitude modulator may define an optical cavity. Furthermore, a resonance of the first ring resonator may be aligned with a lasing wavelength, and the resonance of the first ring resonator and a resonance of the amplitude modulator may be offset from each other. Additionally, modulation of the first ring resonator and the amplitude modulator may be in-phase with each other.Type: ApplicationFiled: July 18, 2018Publication date: January 24, 2019Applicant: Axalume, Inc.Inventors: Jock Bovington, Xuezhe Zheng, Saman Saeedi, Ashok V. Krishnamoorthy
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Publication number: 20190027899Abstract: An optical source may include an optical gain chip that provides an optical signal and that is optically coupled to an SOI chip. The optical gain chip may include a reflective layer. Moreover, the SOI chip may include: a common optical waveguide, a splitter that splits the optical signal into optical signals, a first pair of resonators that are selectively optically coupled to the common optical waveguide and that are configured to perform modulation and filtering of the optical signals, and a first bus optical waveguide that is selectively optically coupled to the first pair of resonators. Furthermore, resonance wavelengths of the resonators may be offset from each other with a (e.g., fixed) separation approximately equal or corresponding to a modulation amplitude, and a reflectivity of the first pair of resonators may be approximately independent of the modulation.Type: ApplicationFiled: July 18, 2018Publication date: January 24, 2019Applicant: Axalume, Inc.Inventors: Ashok V. Krishnamoorthy, Jock Bovington, Xuezhe Zheng, Saman Saeedi
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Patent number: 10109981Abstract: Monolithic asymmetric optical waveguide grating resonators including an asymmetric resonant grating are disposed in a waveguide. A first grating strength is provided along a first grating length, and a second grating strength, higher than the first grating strength, is provided along a second grating length. In advantageous embodiments, the effective refractive index along first grating length is substantially matched to the effective refractive index along second grating length through proper design of waveguide and grating parameters. A well-matched effective index of refraction may permit the resonant grating to operate in a highly asymmetric single longitudinal mode (SLM). In further embodiments, an asymmetric monolithic DFB laser diode includes front and back grating sections having waveguide and grating parameters for highly asymmetric operation.Type: GrantFiled: December 27, 2013Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Matthew Sysak, Jock Bovington
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Patent number: 10014659Abstract: An optical source is described. This optical source includes a set of semiconductor optical amplifiers, with a semiconductor other than silicon, which provides an optical gain medium. In addition, a photonic chip, optically coupled to the set of semiconductor optical amplifiers, includes optical paths. Each of the optical paths includes an optical waveguide and a distributed-Bragg-reflector (DBR) ring resonator. The DBR ring resonator at least partially reflects a given tunable wavelength in an optical signal provided by a given semiconductor optical amplifier. Moreover, the DBR ring resonator includes a different number of grating periods than DBR ring resonators in the remaining optical paths, and the DBR ring resonators in the optical paths have a common radius.Type: GrantFiled: June 15, 2016Date of Patent: July 3, 2018Assignee: Oracle International CorporationInventors: Jock Bovington, Xuezhe Zheng, Ashok V. Krishnamoorthy
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Publication number: 20180115139Abstract: An optical source is described. This optical source includes a set of semiconductor optical amplifiers, with a semiconductor other than silicon, which provides an optical gain medium. In addition, a photonic chip, optically coupled to the set of semiconductor optical amplifiers, includes optical paths. Each of the optical paths includes an optical waveguide and a distributed-Bragg-reflector (DBR) ring resonator. The DBR ring resonator at least partially reflects a given tunable wavelength in an optical signal provided by a given semiconductor optical amplifier. Moreover, the DBR ring resonator includes a different number of grating periods than DBR ring resonators in the remaining optical paths, and the DBR ring resonators in the optical paths have a common radius.Type: ApplicationFiled: June 15, 2016Publication date: April 26, 2018Applicant: Oracle International CorporationInventors: Jock Bovington, Xuezhe Zheng, Ashok V. Krishnamoorthy
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Publication number: 20170227708Abstract: A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.Type: ApplicationFiled: June 3, 2016Publication date: August 10, 2017Applicant: The Regents of the University of CaliforniaInventors: John E. BOWERS, Jock BOVINGTON
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Ultra-broadband photonic integrated circuit platform and ultra-broadband photonic integrated circuit
Patent number: 9612398Abstract: An ultra-broadband photonic integrated circuit platform that combines at least two types of waveguides that each transmit in different, but overlapping, spectral bands on a single chip. By combining the multiple waveguides, the bandwidth of the platform can be extended beyond the bandwidth of either waveguide alone. In an exemplary embodiment, an ultra-broadband photonic integrated circuit includes a nitride-on-insulator (NOI) waveguide configured to transmit optical beams in a first spectral band and a silicon-on-nitride-on-insulator (SONOI) waveguide configured to transmit optical beams in a second band, where the same material serves as the core material in the NOI waveguide and as the cladding material in the SONOI waveguide. In some embodiments, light-emitting devices are bonded to an upper surface of the waveguides. In some embodiments, the circuit includes beam-combining elements so that a single beam combining all of the input wavelengths is output from the circuit.Type: GrantFiled: October 16, 2015Date of Patent: April 4, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Igor Vurgaftman, Jerry R. Meyer, Martijn Heck, Jock Bovington, Alexander Spott, Eric Stanton, John Bowers -
Publication number: 20160380407Abstract: Monolithic asymmetric optical waveguide grating resonators including an asymmetric resonant grating are disposed in a waveguide. A first grating strength is provided along a first grating length, and a second grating strength, higher than the first grating strength, is provided along a second grating length. In advantageous embodiments, the effective refractive index along first grating length is substantially matched to the effective refractive index along second grating length through proper design of waveguide and grating parameters. A well-matched effective index of refraction may permit the resonant grating to operate in a highly asymmetric single longitudinal mode (SLM). In further embodiments, an asymmetric monolithic DFB laser diode includes front and back grating sections having waveguide and grating parameters for highly asymmetric operation.Type: ApplicationFiled: December 27, 2013Publication date: December 29, 2016Inventors: Matthew SYSAK, Jock BOVINGTON
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Patent number: 9360623Abstract: A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.Type: GrantFiled: December 19, 2014Date of Patent: June 7, 2016Assignee: The Regents of the University of CaliforniaInventors: John E. Bowers, Jock Bovington
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Ultra-Broadband Photonic Integrated Circuit Platform and Ultra-Broadband Photonic Integrated Circuit
Publication number: 20160109655Abstract: An ultra-broadband photonic integrated circuit platform that combines at least two types of waveguides that each transmit in different, but overlapping, spectral bands on a single chip. By combining the multiple waveguides, the bandwidth of the platform can be extended beyond the bandwidth of either waveguide alone. In an exemplary embodiment, an ultra-broadband photonic integrated circuit includes a nitride-on-insulator (NOI) waveguide configured to transmit optical beams in a first spectral band and a silicon-on-nitride-on-insulator (SONOI) waveguide configured to transmit optical beams in a second band, where the same material serves as the core material in the NOI waveguide and as the cladding material in the SONOI waveguide. In some embodiments, light-emitting devices are bonded to an upper surface of the waveguides. In some embodiments, the circuit includes beam-combining elements so that a single beam combining all of the input wavelengths is output from the circuit.Type: ApplicationFiled: October 16, 2015Publication date: April 21, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Igor Vurgaftman, Jerry R. Meyer, Martijn Heck, Jock Bovington, Alexander Spott, Eric Stanton, John Bowers -
Patent number: 9285540Abstract: A method for realizing a semiconductor waveguide and an ultra-low-loss dielectric waveguide disposed on the same substrate is disclosed. The method includes forming a partial dielectric waveguide structure on the substrate, wherein the dielectric waveguide is annealed to reduce hydrogen incorporation, and wherein the top cladding of the dielectric waveguide is only partially formed by a first dielectric layer. A second substrate comprising a semiconductor layer having a second dielectric layer disposed on its top surface is bonded to the first substrate such that the first and second dielectric layers collectively form the complete top cladding for the dielectric waveguide. The second substrate is then removed and the semiconductor layer is patterned to define the semiconductor waveguide core.Type: GrantFiled: September 20, 2013Date of Patent: March 15, 2016Assignee: The Regents of the University of CaliforniaInventors: Jared Bauters, John E. Bowers, Jock Bovington, Martijn Heck, Michael Davenport, Daniel Blumenthal, Jonathon Scott Barton
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Publication number: 20150226918Abstract: A method for realizing a semiconductor waveguide and an ultra-low-loss dielectric waveguide disposed on the same substrate is disclosed. The method includes forming a partial dielectric waveguide structure on the substrate, wherein the dielectric waveguide is annealed to reduce hydrogen incorporation, and wherein the top cladding of the dielectric waveguide is only partially formed by a first dielectric layer. A second substrate comprising a semiconductor layer having a second dielectric layer disposed on its top surface is bonded to the first substrate such that the first and second dielectric layers collectively form the complete top cladding for the dielectric waveguide. The second substrate is then removed and the semiconductor layer is patterned to define the semiconductor waveguide core.Type: ApplicationFiled: September 20, 2013Publication date: August 13, 2015Inventors: Jared Bauters, John E. Bowers, Jock Bovington, Martijn Heck, Michael Davenport, Daniel Blumenthal, Jonathon Scott Barton
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Publication number: 20150177458Abstract: A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.Type: ApplicationFiled: December 19, 2014Publication date: June 25, 2015Inventors: John E. BOWERS, Jock BOVINGTON