Patents by Inventor Jodi Grzeskowiak

Jodi Grzeskowiak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391180
    Abstract: In method of patterning a substrate, a first relief pattern is formed based on a first layer deposited over a substrate. Openings in the first relief pattern are filled with a reversal material. The first relief pattern is then removed from the substrate and the reversal material remains on the substrate to define a second relief pattern. A fill material is deposited over the substrate that is in contact with the second relief pattern, and sensitive to a photo-acid generated from a photo-acid generator in the second relief pattern. Selected portions of the second relief pattern are exposed to a first actinic radiation to generate the photo-acid in the selected portions of the second relief pattern. The photo-acid are driven from the selected portions of the second relief pattern into portions of the fill material so that the portions of the fill material to become soluble to a predetermined developer.
    Type: Application
    Filed: April 2, 2021
    Publication date: December 16, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Michael Murphy, Jodi Grzeskowiak, Anton J. deVilliers
  • Patent number: 11201051
    Abstract: Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 14, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Jodi Grzeskowiak, Anton J. Devilliers, Daniel Fulford
  • Publication number: 20210294148
    Abstract: A method of planarizing a substrate includes receiving a substrate having structures formed on a target layer on a working surface of a substrate where the structures and the target layer are formed of different materials. Depositing a grafting material, including a solubility-shifting agent, on the substrate, the grafting material adhering to uncovered surfaces of the target layer without adhering to surfaces of the structures, depositing a fill material on the substrate that covers the grafting material, causing the solubility-shifting agent to diffuse a predetermined distance into the fill material, where the solubility-shifting agent causes the fill material to become insoluble to a predetermined solvent, and using the predetermined solvent to remove soluble portions of the fill material where the remaining portions of the fill material form a surface parallel to the working surface of the substrate.
    Type: Application
    Filed: February 23, 2021
    Publication date: September 23, 2021
    Inventors: Jodi Grzeskowiak, Daniel Fulford, Robert Brandt
  • Publication number: 20210242020
    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Inventors: David L. O'Meara, Eric Chih-Fang Liu, Jodi Grzeskowiak, Anton deVilliers, Akiteru Ko, Anthony Dip
  • Publication number: 20210104609
    Abstract: A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 8, 2021
    Inventors: Anton deVilliers, Jodi Grzeskowiak, Lars Liebmann, Daniel Chanemougame
  • Publication number: 20210098294
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.
    Type: Application
    Filed: September 28, 2020
    Publication date: April 1, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Lars LIEBMANN, Daniel CHANEMOUGAME, Hiroki NIIMI, Kandabara TAPILY, Subhadeep KAL, Jodi GRZESKOWIAK, Anton DEVILLIERS
  • Publication number: 20210098306
    Abstract: A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.
    Type: Application
    Filed: September 2, 2020
    Publication date: April 1, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Hiroaki Niimi, Jodi Grzeskowiak, Daniel Chanemougame, Lars Liebmann, Kandabara Tapily, Subhadeep Kal, Anton J. deVilliers
  • Publication number: 20210088904
    Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Anton J. DEVILLIERS, Jodi GRZESKOWIAK, Daniel FULFORD, Richard A. FARRELL, Jeffrey SMITH
  • Publication number: 20210088907
    Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 25, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jodi GRZESKOWIAK, Anthony SCHEPIS, Anton DEVILLIERS
  • Publication number: 20210082750
    Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Kai-Hung YU, Jodi GRZESKOWIAK, Nicholas JOY, Jeffrey SMITH
  • Publication number: 20210020435
    Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 21, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Daniel FULFORD, Jodi GRZESKOWIAK, Anton J. DEVILLIERS
  • Publication number: 20210020453
    Abstract: The disclosure relates to techniques and methods for planarizing a substrate by amplifying and controlling z-height technology. Variability of z-height can be modeled or measured for each device. A counter height pattern can then be created and processed on a substrate. By using different materials with different etch rates, a planarizing pattern can be transferred to the substrate or system to create a planarized substrate surface for improved lithography. Additionally, a transition region slope can be precisely controlled using the same methods.
    Type: Application
    Filed: February 7, 2020
    Publication date: January 21, 2021
    Inventors: Daniel FULFORD, Jodi GRZESKOWIAK, Anton J. DEVILLIERS
  • Patent number: 10770479
    Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 8, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton deVilliers, Kandabara Tapily, Jodi Grzeskowiak, Kai-Hung Yu
  • Publication number: 20200152448
    Abstract: Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 14, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Jodi GRZESKOWIAK, Anton J. Devilliers, Daniel Fulford
  • Publication number: 20200152472
    Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 14, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Anton DEVILLIERS, Robert BRANDT, Jeffrey SMITH, Jodi GRZESKOWIAK, Daniel FULFORD
  • Publication number: 20190288004
    Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 19, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey SMITH, Anton deVilliers, Kandabara Tapily, Jodi Grzeskowiak, Kai-Hung Yu