Patents by Inventor Jody Alan Fronheiser
Jody Alan Fronheiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11417759Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: June 6, 2019Date of Patent: August 16, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
-
Publication number: 20190363183Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: ApplicationFiled: June 6, 2019Publication date: November 28, 2019Inventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
-
Patent number: 10367089Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: March 27, 2012Date of Patent: July 30, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
-
Publication number: 20160035728Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
-
Patent number: 9190411Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.Type: GrantFiled: June 11, 2013Date of Patent: November 17, 2015Assignee: GlobalFoundries Inc.Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
-
Publication number: 20140361377Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.Type: ApplicationFiled: June 11, 2013Publication date: December 11, 2014Inventors: Ajey Poovannummoottil Jacob, Steven John Bentley, Murat Kerem Akarvardar, Jody Alan Fronheiser, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Toshiharu Nagumo
-
Publication number: 20130075756Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: ApplicationFiled: March 27, 2012Publication date: March 28, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
-
Patent number: 8198650Abstract: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.Type: GrantFiled: December 8, 2008Date of Patent: June 12, 2012Assignee: General Electric CompanyInventors: Stanislav Ivanovich Soloviev, Ho-Young Cha, Peter Micah Sandvik, Alexey Vert, Jody Alan Fronheiser
-
Publication number: 20110221456Abstract: A sensor system, and an associated method for detecting harsh environmental conditions, is provided. The sensor system includes at least one sensor having an electrical sensing element. The electrical sensing element is based on certain classes of composite materials: (a) silicon carbide (SiC); (Mo,W)5Si3C; (Mo,W)Si2; or (b) (Mo,W)5Si3C; (Mo,W)Si2; (Mo,W)5Si3. The sensor system is useful for determining harsh environmental conditions. Gasification systems, which include at least one of the sensor systems are also described.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Applicant: GENERAL ELECTRIC COMPANYInventors: Jody Alan Fronheiser, Don Mark Lipkin, Peter Micah Sandvik, Todd Michael Striker, Martin Mathew Morra
-
Patent number: 7906427Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.Type: GrantFiled: October 14, 2008Date of Patent: March 15, 2011Assignee: General Electric CompanyInventors: Jody Alan Fronheiser, Peter Micah Sandvik, Kevin Sean Matocha, Vinayak Tilak
-
Publication number: 20100140730Abstract: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Stanislav Ivanovich Soloviev, Ho-Young Cha, Peter Micah Sandvik, Alexey Vert, Jody Alan Fronheiser
-
Publication number: 20100093116Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.Type: ApplicationFiled: October 14, 2008Publication date: April 15, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Jody Alan Fronheiser, Peter Micah Sandvik, Kevin Sean Matocha, Vinayak Tilak
-
Patent number: 7691711Abstract: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.Type: GrantFiled: January 31, 2008Date of Patent: April 6, 2010Assignee: General Electric CompanyInventors: Zachary Matthew Stum, Kevin Sean Matocha, Jody Alan Fronheiser, Ljubisa Dragoljub Stevanovic
-
Publication number: 20090267141Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: ApplicationFiled: July 7, 2009Publication date: October 29, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum
-
Patent number: 7595241Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: GrantFiled: August 23, 2006Date of Patent: September 29, 2009Assignee: General Electric CompanyInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum
-
Publication number: 20090194772Abstract: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Zachary Matthew Stum, Kevin Sean Matocha, Jody Alan Fronheiser, Ljubisa Dragoljub Stevanovic
-
Publication number: 20080050876Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum