Abstract: A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state, and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to the output signals of the polynomial counter, implements a predetermined logical mapping of said output signals into a decoded output signal. The clock edge selector, responsive to the decoded output signal of the decode logic, utilizes flip-flops and other logic to generate integer and non-integer multiples of the clock signal. The frequency divider circuit selects either integer or non-integer divisors depending on the informational content of a control signal.