Abstract: A thermal compensating subreflector tracking assembly for a reflector antenna and methods of use. The subreflector tracking assembly provided with a base, an intermediate support and a subreflector mount. The intermediate support coupled to the base, movable normal to the base and the subreflector mount coupled to the intermediate support, movable orthogonal to the intermediate support. The movement in the Z, Y and or Z-axis enabling electrical performance optimizing reflector antenna beam alignment and/or focus adjustments resulting from asymmetric thermal distortion of the reflector antenna.

Abstract: A thermal compensating subreflector tracking assembly for a reflector antenna and methods of use. The subreflector tracking assembly provided with a base, an intermediate support and a subreflector mount. The intermediate support coupled to the base, movable normal to the base and the subreflector mount coupled to the intermediate support, movable orthogonal to the intermediate support. The movement in the Z, Y and or Z-axis enabling electrical performance optimizing reflector antenna beam alignment and/or focus adjustments resulting from asymmetric thermal distortion of the reflector antenna.

Abstract: A line holder for securing a chalking line to a work piece that is to be marked, particularly for diagonal cut lines, in which a planar body engages an end of a chalking line and includes a spaced-apart second opening, through which a spring-biased member extends. The member is joined to the planar body at a fixed end and has a pointed tip at a distal free end. The member is biased to a first position with the tip upwardly of the planar body and is selectively moveable to a second position with the tip extended through the second opening for engaging a work piece to be marked by the chalk line.

Abstract: A transceiver as provided for effectively multiplexing IDE address and data lines with selected ISA address and data lines. Compatibility among the IDE data transfers and ISA functions are achieved by multiplexing the ISA lines that do not involve the ISA refresh of the ISA expanded memory. The transceiver includes an enable input that, when disabled, effectively isolates the IDE data lines from the ISA bus so that IDE data transfers can occur. When the enable input is active, the ISA lines not related to refresh are connected to the IDE data lines so that ISA operations can occur. Furthermore, a directional input is included in the transceiver for allowing a central processing unit to control the ISA when the directional input is active and for allowing a PCI/ISA bridge between the PCI bus and the ISA bus to control the ISA operations included the multiplexing. The result is a rearrangement of the IDE data lines with the ISA bus to eliminate a multitude of pins and connectors.