Abstract: A system and method for delaying power to a computer system. The method includes providing a standby signal. The method further includes receiving a power up signal. The method also includes delaying the power up signal. The method further includes passing the power up signal to the computer system after delaying the power up signal. The system includes a detection circuit and a delay circuit. The detection circuit is configured to receive a standby signal from a power supply. The detection circuit is also configured to output a control signal. The delay circuit is coupled to receive the control signal. The delay circuit is configured to output a delayed control signal for the power supply in response to the control signal after a predetermined period of time.

Abstract: A cooling device detection circuit and method for detecting a cooling device in a computer system. In one embodiment, a cooling device detection circuit includes a detection stage and a power management stage. The detection stage is configured to sense an indication that the cooling device is functioning and to assert a signal if the cooling device is detected. The power management stage is configured to turn off a component cooled by the cooling device if the cooling device is not detected.

Abstract: A circuit and method for reducing voltage oscillations at the output leads of a digital integrated circuit. A circuit for reducing voltage oscillations on the output leads of a digital integrated circuit comprising a positive voltage charge pump unit coupled to an output driver, a negative voltage charge pump unit also coupled to the output driver and a sense and control unit coupled to both the negative voltage charge pump unit and the positive voltage charge pump unit is presented. The sense and control unit is configured to determine whether switching current is present in the source or drain of the output driver. If switching current is present in the source, then the sense and control unit is further configured to connect the positive voltage charge pump unit to the source. If switching current is present in the drain, then the sense and control unit is still further configured to connect the negative voltage charge pump unit to the drain.

Abstract: A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of a data portion of the bus. One embodiment of the computer system includes at least one central processing unit (CPU) and a main memory coupled to a processor bus. The main memory stores data, and the CPU executes instructions stored within the main memory. The processor bus is a split transaction bus. The processor bus is divided into an address bus, a data bus, and a control bus including address, data, and control signal lines, respectively. The CPU and the main memory each include a bus interface, and are coupled to the processor bus via the bus interface. The bus interface includes a transaction queue coupled to an interface unit. The interface unit is coupled to the address, data, and control buses, and performs bus transactions (i.e., read and/or write transactions) upon the processor bus.