Patents by Inventor Joe-Anand Louis-Chandran

Joe-Anand Louis-Chandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit device having I/O structures with reduced input loss
    Patent number: 7012330
    Abstract: The present invention is an input/output (I/O) structure for an integrated circuit device which increases the input signal energy transfer characteristic and allows for increased operating frequency of the device. The I/O structure includes a conductive region in a doped region below a semiconductor bond pad. The I/O structure also includes a tapped region coupled to a supply voltage. The I/O structure may also include an output driver transistor layout with a tapped source region to decrease a parasitic series resistance between a drain region and a source voltage.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: March 14, 2006
    Assignee: Rambus Inc.
    Inventors: Stefanos Sidiropoulos, Joe-Anand Louis-Chandran