Abstract: A sphere mode texture coordinate generator circuit for use in a graphics adapter of a data processing system is disclosed. The circuit includes a set of input multiplexers configured to receive x, y, and z components of a normal vector and a unit vector corresponding to the current vertex. The circuit further includes a set of functional units such as a floating point multiplier, a floating point adder, a floating point compare-to-zero unit, and an inverse square unit. The functional units are configured to receive outputs from the set of multiplexer and are enabled to perform floating point operations on the outputs of the set of multiplexers. A controller or state machine of the circuit is enabled to determine the state of select inputs to each of the set of multiplexers. The controller manages the multiplexer select inputs such that the circuit determines sphere mode texture coordinates in response to receiving the normal vector and the unit vector.

Abstract: A method and apparatus in a geometry engine having a plurality of stages for processing graphics data. An immediate mode data stream is received at a first stage within the plurality of stages. Data from the immediate mode data stream is stored in a storage to build a vertex data structure for processing within the plurality of stages. The vertex data structure is transmitted to the first stage for processing in response to receiving a signal to transmit the vertex data structure. Data for the vertex data structure remains in the storage as default data for a subsequent vertex data structure.

Abstract: A method and system for sequentially addressing multiple components, having a limited number of externally available address lines, on a communication bus. The method and system employs an addressing scheme in combination with a specific interconnection of the components. This combination enables each of the components to be addressed in a sequential fashion by dynamically altering their address. Thus, allowing a virtually unlimited number of components to be coupled to the communication bus without the traditional concerns over the number of externally available address lines.

Abstract: An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass t