Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.

Abstract: A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.

Abstract: A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.

Abstract: This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.

Abstract: A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.