Patents by Inventor Joe D Guerra

Joe D Guerra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100146782
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Application
    Filed: February 23, 2010
    Publication date: June 17, 2010
    Applicant: MULTI-FINELINE ELECTRONIX, INC.
    Inventors: Ronald W. Whittaker, Joe D. Guerra, Ciprian Marcoci
  • Publication number: 20100127814
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Application
    Filed: December 16, 2009
    Publication date: May 27, 2010
    Applicant: Multi-Fineline Electronix, Inc.
    Inventors: Ronald W. Whittaker, Joe D. Guerra, Ciprian Marcoci
  • Patent number: 7690110
    Abstract: A method for making plural plated through holes in a single circuit board via is provided. The method includes plating copper in the walls of said circuit board via to form a first plated through hole and applying a thin layer of first adhesive promotor to the surface of said plated via. The method further includes vacuum depositing an organic layer having a high dielectric strength unto said layer of first adhesive promoter and applying a second layer of adhesive promoter over said organic layer. The method even further includes plating copper over said second layer of adhesive promoter to form a second plated through hole in said circuit board via.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: April 6, 2010
    Assignee: Multi-Fineline Electronix, Inc.
    Inventors: Ronald W. Whittaker, Joe D Guerra, Ciprian Marcoci
  • Patent number: 7656263
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 2, 2010
    Assignee: Multi-Fineline Electronix, Inc.
    Inventors: Ronald W. Whittaker, Joe D. Guerra, Ciprian Marcoci
  • Patent number: 7602272
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: October 13, 2009
    Assignee: Multi-Fineline Electronix, Inc.
    Inventors: Ronald W. Whittaker, Joe D Guerra, Ciprian Marcoci
  • Publication number: 20090015364
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Application
    Filed: September 18, 2008
    Publication date: January 15, 2009
    Inventors: Ronald W. Whittaker, Joe D. Guerra, Ciprian Marcoci
  • Patent number: 7436282
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: October 14, 2008
    Assignee: Multi-Fineline Electronix, Inc.
    Inventors: Ronald W. Whittaker, Joe D. Guerra, Ciprian Marcoci
  • Patent number: 7271697
    Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: September 18, 2007
    Assignee: Multi-Fineline Electronix
    Inventors: Ronald W. Whittaker, Joe D Guerra, Ciprian Marcoci