Abstract: Externally formed connections are made to a wafer scale integration (WSI) type of semiconductor device to accomplish wafer level defect avoidance and includes the utilization of a relatively small external shorting block or patch circuit for implementing predetermined shorting connections, such as jumpers, on a diode decoder circuit on the wafer to program an address of a defective primary site into a register associated with a predetermined spare site for substituting the spare site for a defective primary site when power is applied to a fully processed WSI wafer having (n+r) sites including (n) primary sites and (r) spare sites and where n primary sites are required to perform a predetermined circuit function.

Abstract: A method and apparatus for providing a flexible and adaptive communication link from one of four wafer input/output channels respectively located on each of four sides of a silicon wafer to a predetermined internal memory-logic site includes in a matrix array of indentical memory-logic sites located on the wafer. A new linkage path can be formed, if necessary, each time a memory-logic is accessed. Each memory-logic site is capable of communicating with any of its neighboring sites, which includes not only its four opposing sides, but also its four adjacent diagonal sites, by one of a plurality of input/output site ports. A programmed external controller coupled to a computer, for example, works from the edge of the wafer through the selected wafer input/output channel and links to any designated memory-logic site for the purpose of data storage, data retrieval or test.

Abstract: Wafer scale integrated circuit apparatus wherein a full wafer scale semiconductor integrated wafer is adhesively secured to an essentially flat heat conducting non-metallic base member with the wafer and base member having coefficients of thermal expansion approximately equal to one another. A cable adapter assembly connected to an edge of the base member secures one or more multiconductor flat cables in position such that the conductors thereof, by means of a clamping arrangement make positive pressure contacts with contact points connected to electronic circuitry of the semiconductor wafer. Another wafer may be placed on an opposed surface of the base member and a second cable adapter assembly may be utilized to secure another multiconductor flat cable for making interconnection between contact points of the wafer on one surface with contact points of the wafer on the opposed surface of the base member.

Abstract: A memory sub-array having a single volatile memory cell and an array of nonvolatile memory cells. The volatile memory cell includes a static flip-flop circuit and each memory cell of the nonvolatile memory cell array includes a pair of nonvolatile memory transistors that store information in accordance with the state of the transistor threshold voltage.

Abstract: An MNOS memory array including circuitry to permit all of the memory devices comprising the array to be addressed for purposes of clearing the array by a block select and a clear signal as disclosed. The circuitry is arranged such that a plurality of arrays may be interconnected to form a large block oriented memory system with all blocks utilizing a common clear signal.