Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have non-volatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.

Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have nonvolatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.

Abstract: A data processing system which has an interface circuit that interfaces the data processing system to input devices. The interface includes an input means such as a pad for conducting signal levels from the interface devices to the data processing system. A digitizer, such as a Schmitt trigger, digitizes the signal levels to signal levels that are acceptable by the data processing system. An output line conditioner conditions the data lines that are connected to the digitizers to prevent overdriving of the data lines by the digitizers. Line drivers are used for driving the digitized system on the data lines throughout the data processing system.

Abstract: A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.

Abstract: A combination of logic circuits perform logical operations on data and include a plurality of shift register latches. Each shift register latch includes a latch means for the storing of data, an isolation means for isolating the latch means from data and clock signals connected logic circuits when the isolation means is at a first state, and for conducting data to the latch means when the isolation means is at a second state. Each shift register latch also includes a power reduction means for reducing the power consumed by the isolation means and the latch means.

Abstract: A digital computing system is disclosed having a monolithic microprocessor, a versatile input/output subsystem, a multi-medium capability. In the memory subsystem, a balanced mix of dynamic RAM, P-channel MOS ROM and N-channel MOS ROM are included to minimize cost without sacrificing performance. In the video display subsystem, a monolithic video display processor performs all RAM access functions, in addition to composite video generation. The resultant composite video signal, which may include audio and external video information, can be applied directly to a video monitor or RF modulated for use by a television receiver.

Abstract: A calculator printer interface performs control of a printer's segmenting of symbols in a string of numeral words from an LSI/MOS calculator chip. The output from the LSI/MOS calculator chip is a sequence of multibit data words including a leading decimal point position word indicating the position of a decimal point followed by numeral words indicating respective numerals of a number to be printed. The decimal point position word is decoded and the numeral words are entered into a shift register together with a word indicating a decimal point in the position within the sequence indicated by the decimal point position word. When the number is printed, words indicating where commas are to appear are inserted into the sequence of data words outputted from the shift register by counting by three after the word indicating a decimal. Commas and zeros occurring after the last nonzero numeral word in the sequence are suppressed.