Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

Abstract: An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

Abstract: A photonic connector comprises a first ferrule having a first plurality of optical fibers. A membrane cover is attached to the first ferrule and covers ends of the first plurality of optical fibers. Once the first ferrule is mated with a second ferrule having a second plurality of optical fibers, the membrane cover is pierced by the first plurality of optical fibers, the second plurality of optical fibers, or both.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

Abstract: An apparatus for testing integrated circuits (ICs), comprising a first thermal contact structure having a first surface to interface with a heat source, the first surface is opposite a second surface. A second thermal contact structure is above the first thermal contact structure and separated therefrom. The second thermal contact structure has a third surface to interface with a cold mass. The third surface is opposite a fourth surface, and the fourth surface is opposite the second surface. A variable-resistance thermal interface (VRTI) structure is between the first and second thermal contact structures. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.

Abstract: Space transformation technology for probe cards at sort is disclosed. In one example, a space transformer transforms a pitch of electrical contacts from a first distribution to a second distribution. The space transformer comprises a substrate with opposite first and second sides; and vias extending through the substrate between the first and second sides and oriented at different angles with respect to one another. In one example, a tester system or probe card for a die comprises a printed circuit board (PCB) with pads having a pad pitch; and a space transformer operatively coupled to the PCB, and having vias extending from the pads of the PCB through the space transformer at different angles with respect to one another and configured to electrically connect to contacts on the die having a contact pitch different than the pad pitch.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

Abstract: Electronic device assemblies and methods including an organic substrate based space transformer are described. One assembly includes a space transformer comprising an organic substrate. The assembly also includes a carrier on which the space transformer is positioned, and a clamp positioned to couple the space transformer to the carrier. The assembly also includes a probe array positioned on the space transformer, wherein the space transformer is positioned between the probe array and the carrier. The assembly also includes a printed circuit board, wherein the carrier is positioned between the printed circuit board and the space transformer. The assembly also includes electrical connections to electrically couple the space transformer to the printed circuit board. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure are directed to interconnects that include liquid metal, and associated techniques and configurations. The individual interconnects may electrically couple a contact of a printed circuit board (PCB) to a contact of a device under test (DUT). The interconnect may be disposed in or on the PCB. In various embodiments, the interconnect may include a carrier that defines a well (e.g., an opening in the carrier), and the liquid metal may be disposed in the well. In some embodiments, the contact of the DUT, or a contact of an intermediary device, may extend into the well and directly contact the liquid metal. In other embodiments, a flex circuit may be disposed over the well to seal the well. The flex circuit may include a conductive pad to electrically couple the liquid metal to the contact of the DUT. Other embodiments may be described and claimed.

Abstract: A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.

Abstract: Electronic device assemblies and methods including an organic substrate based space transformer are described. One assembly includes a space transformer comprising an organic substrate. The assembly also includes a carrier on which the space transformer is positioned, and a clamp positioned to couple the space transformer to the carrier. The assembly also includes a probe array positioned on the space transformer, wherein the space transformer is positioned between the probe array and the carrier. The assembly also includes a printed circuit board, wherein the carrier is positioned between the printed circuit board and the space transformer. The assembly also includes electrical connections to electrically couple the space transformer to the printed circuit board. Other embodiments are described and claimed.

Abstract: Embodiments of the present disclosure are directed to interconnects that include liquid metal, and associated techniques and configurations. The individual interconnects may electrically couple a contact of a printed circuit board (PCB) to a contact of a device under test (DUT). The interconnect may be disposed in or on the PCB. In various embodiments, the interconnect may include a carrier that defines a well (e.g., an opening in the carrier), and the liquid metal may be disposed in the well. In some embodiments, the contact of the DUT, or a contact of an intermediary device, may extend into the well and directly contact the liquid metal. In other embodiments, a flex circuit may be disposed over the well to seal the well. The flex circuit may include a conductive pad to electrically couple the liquid metal to the contact of the DUT. Other embodiments may be described and claimed.