Patents by Inventor Joe G. Tran
Joe G. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9035399Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.Type: GrantFiled: March 25, 2010Date of Patent: May 19, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
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Patent number: 7998865Abstract: A system (500) removes wafer edge residue from a target wafer (508). A wafer holding mechanism (502) holds and rotates the target wafer (508). A residue remover mechanism (504) mechanically interacts or abrades an edge surface of the target wafer (508) and removes strongly adhered residue from the edge surface of the target wafer (508). The residue remover mechanism (504) controls coverage of the mechanical interaction and magnitude of the mechanical interaction.Type: GrantFiled: May 31, 2005Date of Patent: August 16, 2011Assignee: Texas Instruments IncorporatedInventors: Joe G. Tran, Brian K. Kirkpatrick, Alfred J. Griffin, Jr.
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Patent number: 7943499Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.Type: GrantFiled: October 21, 2009Date of Patent: May 17, 2011Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
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Publication number: 20100176462Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.Type: ApplicationFiled: March 25, 2010Publication date: July 15, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
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Patent number: 7732312Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.Type: GrantFiled: January 24, 2006Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
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Patent number: 7732313Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.Type: GrantFiled: January 5, 2009Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
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Patent number: 7727842Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.Type: GrantFiled: April 27, 2007Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
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Publication number: 20100041231Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.Type: ApplicationFiled: October 21, 2009Publication date: February 18, 2010Applicant: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Yaw S. Obeng, Ping Jiang, Joe G. Tran
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Publication number: 20090111224Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.Type: ApplicationFiled: January 5, 2009Publication date: April 30, 2009Applicant: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Yew S. Obeng, Ping Jiang, Joe G. Tran
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Patent number: 7498264Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate electrodes 150 that are, in turn, located over a microelectronics substrate 110. The gate electrodes 150 have a doped region 170a located between them. A portion of the spacer material 160 is removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material 160. The method further comprises etching a remaining portion of the spacer material 163, 165, 168 to form spacer sidewalls 163, 165, 168 on the gate electrodes 150. The etching exposes a surface of the gate electrodes 150 and leaves a portion of the spacer material 168 over the doped region 170a. Metal is then incorporated into the gate electrodes 150 to form silicided gate electrodes 150.Type: GrantFiled: July 7, 2005Date of Patent: March 3, 2009Assignee: Texas Instruments IncorporatedInventors: Freidoon Mehard, Shafoeng Yu, Joe G. Tran
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Publication number: 20080265344Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
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Patent number: 7396716Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.Type: GrantFiled: August 11, 2005Date of Patent: July 8, 2008Assignee: Texas Instruments IncorporatedInventors: Freidoon Mehrad, Shaofeng Yu, Joe G. Tran
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Patent number: 7186651Abstract: A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.Type: GrantFiled: October 30, 2003Date of Patent: March 6, 2007Assignee: Texas Instruments IncorporatedInventors: Joe G. Tran, Chad J. Kaneshige, Brian K. Kirkpatrick
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Patent number: 6686283Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.Type: GrantFiled: February 4, 2000Date of Patent: February 3, 2004Assignee: Texas Instruments IncorporatedInventors: Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan, Janice D. Makos, Arun Sivasothy, Troy A. Yocum, Jaideep Mavoori, Wayne A. Bather, Joe G. Tran, Ju-Ai Ruan, Michelle L. Hartsell, Gregory B. Shinn