Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A computer system, method, and controller bus agent for control access to a computer bus. The computer system includes a parallel architecture in which plural bus agents are directly coupled to the computer bus. Each bus agent includes plural bus requester ports each coupled to a different bus requester. As such, the computer system employs a relatively flat, parallel architecture that handles bus requests from the bus requesters in parallel. The controller bus agent includes an internal arbiter and an external arbiter. The internal arbiter arbitrates between bus requests received from the plural bus requesters coupled to the controller bus agent. The external arbiter arbitrates between the bus requests received from other bus agents and from the internal arbiter.

Abstract: A method and system interfaces a plurality of bus requesters with a computer bus having a bus bandwidth. The bus bandwidth is apportioned among the plurality of bus requesters by assigning to a selected bus requester a portion of the bus bandwidth based on how much the selected bus requester used the bus during a defined period. A bus controller determines how much the selected bus requester used the bus during the defined period by monitoring the use of the bus requester during the defined period. The bus controller assigns an initial bus bandwidth portion and a target use bandwidth portion. The bus controller compares how much the selected bus requester used the bus during the defined period to the target use bandwidth portion assigned to the selected bus requester.

Abstract: A computer system, method, and controller bus agent for control access to a computer bus. The computer system includes a parallel architecture in which plural bus agents are directly coupled to the computer bus. Each bus agent includes plural bus requester ports each coupled to a different bus requester. As such, the computer system employs a relatively flat, parallel architecture that handles bus requests from the bus requesters in parallel. The controller bus agent includes an internal arbiter and an external arbiter. The internal arbiter arbitrates between bus requests received from the plural bus requesters coupled to the controller bus agent. The external arbiter arbitrates between the bus requests received from other bus agents and from the internal arbiter.

Abstract: A method and system interfaces a plurality of bus requesters with a computer bus having a bus bandwidth. The bus bandwidth is apportioned among the plurality of bus requesters by assigning to a selected bus requester a portion of the bus bandwidth based on how much the selected bus requester used the bus during a defined period. A bus controller determines how much the selected bus requester used the bus during the fine period by monitoring the use of the bus requester during the defined period. The bus controller assigns an initial bus bandwidth portion and a target use bandwidth portion. The bus controller compares how much the selected bus requester used the bus during the defined period to the target use bandwidth portion assigned to the selected bus requester.