Abstract: A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N− well in a P− doped silicon substrate. A patterned Si3N4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N− base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P++ doped emitter and collector for the L-PNP. The emitter junction depth xj intersects the highly doped N+ buried base region. This N+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP.

Abstract: A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N.sup.- well in a P.sup.- doped silicon substrate. A patterned Si.sub.3 N.sub.4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N.sup.- base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P.sup.++ doped emitter and collector for the L-PNP. The emitter junction depth x.sub.j intersects the highly doped N.sup.+ buried base region. This N.sup.+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP.