Abstract: A multi-level conductive interconnection for an integrated circuit with an antifuse device is formed, in and on a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. The antifuse device is formed from a thin dielectric between a first and second conductor and is connected to the integrated circuit, and is also connected to a ground reference through a silicon junction in the substrate. The large contact pad area is formed with a layer of metal, and is connected to the integrated circuit through the antifuse device, wherein the antifuse device electrically isolates the contact pad and the integrated circuit to prevent charge build-up during subsequent processing. There is further processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the antifuse device prevents charge build-up.

Abstract: A method of forming an integrated circuit field effect transistor with surface counter-doped lightly doped drain regions is described. A gate silicon oxide layer is formed on the silicon substrate. A layer of polysilicon is deposited over the gate silicon oxide layer and etched to form a gate electrode structure. A first ion implantation is performed at a tilt angle to form lightly doped drain regions in the semiconductor substrate wherein the lightly doped drain regions are partially overlapped by the gate electrode structure. A second ion implantation is performed at a larger tilt angle and lower energy than the first ion implantation wherein the second ion implantation counter-dopes the surface of the lightly doped drain regions to form a very lightly doped drain layer thus making the lightly doped drain regions buried regions.

Abstract: A circuit for protecting a CMOS device against execssive voltages has two SCR circuits in which the bipolar transistors are formed as parasitic devices. One SCR circuit is connected between a line to be protected and one power supply point and the other SCR circuit is connected between the line to be protected and the other power supply point. The power supply points form sinks for currents associated with excessive voltages, and they form reference potential points for establishing the voltage at which an SCR turns on. A semiconductor device having an n-substrate has three p-wells. The center p-well (as seen in section) forms part of two vertical transistors, one for each of the two SCR's. Each outer p-well cooperates with the center p-well and the intervening substrate to form a lateral transistor for one of the SCR's. These transistors use shared semiconductor regions that establish the base to collector interconnections of an SCR.