Patents by Inventor Joe Lamb

Joe Lamb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Engineered substrates for use in crystalline-nitride based devices
    Patent number: 9761671
    Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 12, 2017
    Assignee: Veeco Instruments, Inc.
    Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
  • ENGINEERED SUBSTRATES FOR USE IN CRYSTALLINE-NITRIDE BASED DEVICES
    Publication number: 20150187888
    Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
    Type: Application
    Filed: December 30, 2014
    Publication date: July 2, 2015
    Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
  • Pseudo-relative mode WRED/tail drop mechanism
    Patent number: 8948011
    Abstract: A buffer memory can be configured to temporarily store data in a number of queues. A processor can be configured to measure a fullness of the buffer memory. The processor can be configured to adjust thresholds and drop profiles based on a measured global resource usage for a weighted random early detection (WRED) technique with less resources than a conventional.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: February 3, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Joe Lamb, Benjamin Findlen
  • PSEUDO-RELATIVE MODE WRED/TAIL DROP MECHANISM
    Publication number: 20130235725
    Abstract: A buffer memory can be configured to temporarily store data in a number of queues. A processor can be configured to measure a fullness of the buffer memory. The processor can be configured to adjust thresholds and drop profiles based on a measured global resource usage for a weighted random early detection (WRED) technique with less resources than a conventional.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Joe LAMB, Benjamin Findlen
  • Pseudo-relative mode WRED/tail drop mechanism
    Patent number: 8441925
    Abstract: A buffer memory can be configured to temporarily store data in a number of queues. A processor can be configured to measure a fullness of the buffer memory. The processor can be configured to adjust thresholds and drop profiles based on a measured global resource usage for a weighted random early detection (WRED) technique with less resources than a conventional.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: May 14, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Joe Lamb, Benjamin Findlen
  • Mid-filament spacer
    Patent number: D893088
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: August 11, 2020
    Assignee: Veeco Instruments Inc.
    Inventors: Premkumar Suhandira Viran, Hao Chen, Joe Lamb