Abstract: A cache controller of a hybrid write back/write through cache of a uniprocessor system is provided with state transition and complimentary logic that implements a streamlined (modified, exclusive, shared and invalid) MESI cache coherency protocol, (modified, exclusive, pseudo shared and invalid) ME.SIGMA.I, having a pseudo shared state ".SIGMA.". Under the streamlined ME.SIGMA.I, a cache line will enter the .SIGMA. state only through allocation. From the .SIGMA. state, the cache line will remain in the .SIGMA. state when it is read, written into, or snoop-inquired, and it will transition into the I state when it is snoop-invalidated. Additionally, if a cache line in the .SIGMA. state is written into, the cache controller will always cause the data to be written to memory, effectively treating the cache line as a dedicated write through cache line.