Abstract: An electronic device incorporates a linear voltage regulator circuit which includes an external pass transistor that does not rely on internal compensation, provides high gain, and exhibits reduce silicon area and power requirements. Circuits according to the present invention provide sufficient bandwidth with an error amplifier and drive capability to keep any secondary poles sufficiently far from the unity gain bandwidth (UGB) while maintaining good power supply rejection.

Abstract: A linear voltage regulator circuit includes an external pass transistor that does not rely on internal compensation, provides high gain, and exhibits reduce silicon area and power requirements. Circuits according to the present invention provide sufficient bandwidth with an error amplifier and drive capability to keep any secondary poles sufficiently far from the unity gain bandwidth (UGB) while maintaining good power supply rejection.

Abstract: A high speed analog timing and gain feedback control methods and a low power analog tracking timing and gain feedback apparatus are provided for data detection, such as, partial-response maximum-likelihood (PRML) data detection in a direct access storage device (DASD). The interleaved gain and timing tracking control circuit includes an even interleave gain and timing tracking control providing an even interleave gain error signal and an even interleave timing error signal; and an odd interleave gain and timing tracking control providing an odd interleave gain error signal and an odd interleave timing error signal. The even interleave gain error signal and the odd interleave gain error signal are combined to provide a resulting gain control signal. The even interleave timing error signal and the odd interleave timing error signal are combined to provide a resulting timing control signal.

Abstract: A target specific folded analog to digital converter (ADC) is provided, such as for use in a data detection channel in a direct access storage device (DASD). The high speed analog to digital converter (ADC) includes a digital signal decoder for decoding specific target levels of an analog signal. An analog to digital converter section of the ADC converts an analog error signal of the analog signal to digital decoder outputs representing the analog error signal.

Abstract: A direct access storage device includes at least one disk mounted for rotation about an axis and having opposed disk surfaces for storing data. A magneto-resistive (MR) transducer head is mounted for movement across each respective disk surface for writing to and for reading data signals from the disk surface. Each MR transducer head includes a write element and a read element. A preamplifier, associated with the MR transducer head, amplifies read and write signals of the read element and the write element. A flex cable couples the read and write signals between the preamplifier and the MR transducer heads. The flex cable includes a common read return signal line for each sequential pair of the MR transducer heads.

Abstract: Apparatus and method of data recovery are provided for data detection in a partial-response (PR) data channel. The PR data channel includes an analog-to-digital converter (ADC) for providing digital samples of a readback data signal and a voltage controlled oscillator (VCO) timing control coupled to the ADC. A data recovery procedure (DRP) is established responsive to a detected readback error. Using amplitude offset circuitry, amplitude of the readback data signal is selectively adjusted responsive to the detected readback error; and using gain control, a correction current applied to the VCO timing control is changed responsive to the detected readback error.

Abstract: A method and apparatus is disclosed for adaptively controlling the biasing current applied to magnetoresistive (MR) read heads within a magnetic disk drive to provide optimized bias for each head/disk/channel component combination. An optimized bias current for each head is ascertained and stored on the disk surface at the time of manufacture. During each power up operation the values are transferred to random access memory which is accessed during the execution of each head switch command to apply bias current in accordance with the optimized value to the active MR head. Periodic reoptimization and updating of the stored values is effected by general error measurement circuitry that forms a part of the device control system and is invoked to perform the reoptimization upon the occurrence of an event such as a predetermined duration of power on operation subsequent to the last reoptimization procedure.