Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: An integrated circuit including a tunable capacitance multiplier. The integrated circuit includes a reference capacitor and a current source arrangement coupled in parallel to the reference capacitor. The current source arrangement can include a plurality of current sources that are switchably coupled to the reference capacitor in a manner that causes the capacitance of the reference capacitor to vary based on which current sources are coupled thereto. The current sources can be current mirror arrangements of other suitable current sources. The gain factors of the current sources are configured to establish the capacitance variability range and the incremental variance steps therein. In phase-locked loop (PLL) applications, the tunable capacitance multiplier is used to replace the main loop filter capacitor to provide a variable loop bandwidth, thus allowing relatively large values of capacitance to be realized using a relatively small physical capacitor.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: Phase port gain compensating circuitry is coupled to the phase modulation summing circuit and voltage controlled oscillator (VCO) gain compensating circuitry is coupled to the frequency control terminal of the VCO. Compensator control circuitry utilizes divider ratio control information to control the characteristics of the two compensators to compensate for otherwise undesirable effects on the phase-locked loop response parameters caused by changes in the divider ratio and in the VCO gain.

Abstract: A corner mounted tray is essentially triangular in shape and comprises a perforate bottom wall, upstanding side and front walls and is releasably attached to a vertical wall by a mortise and tenon type connection. The connection includes a relatively narrow segment adhesively affixed on the back wall thereof to the vertical wall and providing, on the front wall thereof, one or more shoulder forming elements. The side walls of the tray provide recesses for receiving the shoulder forming elements and supporting the tray thereon.