Patents by Inventor Joe Macri

Joe Macri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120096218
    Abstract: The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 19, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Sagheer Ahmad, Eric Scott, Joe Macri, Dan Shimizu
  • Patent number: 8099638
    Abstract: The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory client control logic configured to use the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 17, 2012
    Assignee: ATI Technologies ULC
    Inventors: Sagheer Ahmad, Eric Scott, Joe Macri, Dan Shimizu
  • Patent number: 7227376
    Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: June 5, 2007
    Assignee: ATI Technologies Inc.
    Inventors: Sagheer Ahmad, Lin Chen, Sam Huynh, Shu-Shia Chow, Joe Macri
  • Publication number: 20060115016
    Abstract: Methods and apparatus for transmitting and receiving data in a memory interface are disclosed. The apparatus include a programmable transceiver having a variable duty cycle control, with the transceiver having at least one of a programmable variable duty cycle receiver and a programmable variable duty cycle transmitter. The receiver and the transmitter are both responsive to variable duty cycle control data and operate to vary a duty cycle of one of incoming and outgoing data. By providing programmability to the data duty cycle, the transceiver can optimally accommodate different memory device standards.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 1, 2006
    Applicant: ATI Technologies Inc.
    Inventors: Lin Chen, Sam Huynh, Joe Macri
  • Publication number: 20060106948
    Abstract: The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory client control logic configured to use the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Applicant: ATI Technologies, Inc.
    Inventors: Sagheer Ahmad, Eric Scott, Joe Macri, Dan Shimizu
  • Publication number: 20060097749
    Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 11, 2006
    Applicant: ATI Technologies, Inc.
    Inventors: Sagheer Ahmad, Lin Chen, Sam Huynh, Shu-Shia Chow, Joe Macri