Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Abstract: A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract: A stencil mask (12 or 12′) has both a thin membrane layer (106) and a stress controlled layer (104) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer (106) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer (104) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics (30) onto resist (44) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.