Patents by Inventor Joe Rowlands
Joe Rowlands has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10613616Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: April 7, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10564703Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: February 18, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10564704Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: February 23, 2018Date of Patent: February 18, 2020Assignee: NetSpeed Systems, Inc.Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 10452124Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.Type: GrantFiled: September 11, 2017Date of Patent: October 22, 2019Inventors: James A. Bauman, Joe Rowlands, Sailesh Kumar
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Patent number: 9830265Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.Type: GrantFiled: November 20, 2013Date of Patent: November 28, 2017Assignee: NetSpeed Systems, Inc.Inventors: Joe Rowlands, Sailesh Kumar
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Patent number: 9590813Abstract: Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein.Type: GrantFiled: September 14, 2016Date of Patent: March 7, 2017Assignee: NetSpeed SystemsInventors: Sailesh Kumar, Eric Norige, Joe Rowlands, Joji Philip
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Patent number: 9535848Abstract: Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation resulting. In example implementations, when an address is replacing another address, the evicted address does not necessarily map to the same places as the new address. Example implementations attempt to conduct a run through of the cache coherent directory with the new entry such that the evicted address can find an empty entry in the directory and fill the empty entry.Type: GrantFiled: June 18, 2014Date of Patent: January 3, 2017Assignee: NetSpeed SystemsInventors: Joe Rowlands, Sailesh Kumar
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Patent number: 9473388Abstract: Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein.Type: GrantFiled: August 7, 2013Date of Patent: October 18, 2016Assignee: NETSPEED SYSTEMSInventors: Sailesh Kumar, Eric Norige, Joe Rowlands, Joji Philip
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Patent number: 9244845Abstract: The present disclosure is directed to hardware hash tables, and more specifically, to generation of a cache coherent system such as in a Network on Chip (NoC). The present disclosure is further directed to a directory structure that includes a new field, referred to, for instance as, encoded value, which indicates the original owner of a dirty line. As an original holder may have held or modified the original line, by tracking the original holder, example implementations can track the agents that are potentially dirty, as the encoded value can indicate the agent with the most recently unique line, which can then be shared with the other agents.Type: GrantFiled: May 12, 2014Date of Patent: January 26, 2016Assignee: NetSpeed SystemsInventors: Joe Rowlands, Sailesh Kumar
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Patent number: 9223711Abstract: Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way Ci is a set-associative table with N sets, where each set has an associativity of A, where A is an integer greater than or equal to 2.Type: GrantFiled: August 13, 2013Date of Patent: December 29, 2015Assignee: NetSpeed SystemsInventors: Joji Philip, Sailesh Kumar, Joe Rowlands
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Publication number: 20150370720Abstract: Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation resulting. In example implementations, when an address is replacing another address, the evicted address does not necessarily map to the same places as the new address. Example implementations attempt to conduct a run through of the cache coherent directory with the new entry such that the evicted address can find an empty entry in the directory and fill the empty entry.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Joe Rowlands, Sailesh Kumar
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Publication number: 20150324288Abstract: The present disclosure is directed to hardware hash tables, and more specifically, to generation of a cache coherent system such as in a Network on Chip (NoC). The present disclosure is further directed to a directory structure that includes a new field, referred to, for instance as, encoded value, which indicates the original owner of a dirty line. As an original holder may have held or modified the original line, by tracking the original holder, example implementations can track the agents that are potentially dirty, as the encoded value can indicate the agent with the most recently unique line, which can then be shared with the other agents.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: NetSpeed SystemsInventors: Joe Rowlands, Sailesh Kumar
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Patent number: 7802073Abstract: The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.Type: GrantFiled: July 23, 2007Date of Patent: September 21, 2010Assignee: Oracle America, Inc.Inventors: Yu Qing Cheng, John Gregory Favor, Carlos Puchol, Seungyoon Peter Song, Peter Glaskowsky, Laurent Moll, Joe Rowlands, Donald Alpert