Patents by Inventor Joe Steinberg

Joe Steinberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121276
    Abstract: This disclosure describes embodiments of systems, methods, and non-transitory computer-readable storage media that can solve one or more of the foregoing (or other problems) in the art in addition to providing other benefits by applying customized security limitations to a secure digital account, and removing the security limitations based on efficiently verifying personal identity information associated with the secure digital account. For example, the disclosed system can receive a user interaction associated with a secure digital account and determine a fraud risk score corresponding to the interaction. The system can then assign the secure digital account a security tier and apply appropriate security limitations based on the security tier that corresponds with a determined risk of fraud.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 11, 2024
    Inventors: Joe Levering, Ryan Bahniuk, Lace Cheung, Kevin Shu, Jocelyn Takahashi, Dain Hall, Jeremy Steinberg, Varun Rai, Charles Kirk
  • Patent number: 5024972
    Abstract: A polysilicon layer may need to have electrical characteristics which are relatively uniform from wafer to wafer. The use of polysilicon as a resistor is one such example. In order to obtain the requisite uniformity, the temperature of the wafers which are receiving the polysilicon must all be the same within a tight tolerance. The reaction takes place in a furnace which takes a long time to reach the requisite temperature tolerance. While the furnace is stabilizing the temperature, oxide, which is an insulator, is growing on the contact locations of the various substrates. To minimize the deleterious oxide formation, a thin layer of polysilicon is deposited at a time significantly prior to the time that the furnace stabilizes which ensures a good, low-resistance contact. The remainder of the polysilicon is then deposited on the thin layer of polysilicon after the temperature has stabilized to obtain the requisite wafer-to-wafer resistance uniformity.
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: June 18, 1991
    Assignee: Motorola, Inc.
    Inventors: Gary A. DePinto, Joe Steinberg, John G. Franka, Michael R. Cherniawski
  • Patent number: 4662956
    Abstract: A method for the prevention of dopant diffusion from the back side of a doped semiconductor substrate during epitaxial layer growth. The entire surface of the substrate is first covered with a cleanly etchable material. Around the entire first layer is formed a second dopant diffusion barrier layer. The front sides of the layers are then selectively etched away to expose the front side of the substrate upon which the epitaxial layer will be grown without contamination of dopant diffusion from the sealed back side of the substrate.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: May 5, 1987
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, Joe Steinberg, H. Scott Morgan