Patents by Inventor Joe Trogolo
Joe Trogolo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8110857Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: GrantFiled: February 26, 2010Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Publication number: 20100155789Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: ApplicationFiled: February 26, 2010Publication date: June 24, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Patent number: 7704813Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: GrantFiled: November 1, 2007Date of Patent: April 27, 2010Assignee: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
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Patent number: 7670888Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: GrantFiled: April 11, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Publication number: 20080251818Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Publication number: 20080090346Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: ApplicationFiled: November 1, 2007Publication date: April 17, 2008Applicant: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
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Patent number: 7312481Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: GrantFiled: October 1, 2004Date of Patent: December 25, 2007Assignee: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
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Publication number: 20070205435Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: ApplicationFiled: May 8, 2007Publication date: September 6, 2007Applicant: Texas Instruments IncorporatedInventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Patent number: 7226835Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: GrantFiled: July 15, 2002Date of Patent: June 5, 2007Assignee: Texas Instruments IncorporatedInventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Publication number: 20060071247Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: ApplicationFiled: October 1, 2004Publication date: April 6, 2006Applicant: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
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Publication number: 20050127409Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: ApplicationFiled: January 25, 2005Publication date: June 16, 2005Inventors: Henry Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
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Publication number: 20050087812Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.Type: ApplicationFiled: November 22, 2004Publication date: April 28, 2005Inventors: Joe Trogolo, William Loftin, William Kyser
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Patent number: 6867100Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: GrantFiled: December 19, 2002Date of Patent: March 15, 2005Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
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Publication number: 20040007716Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Publication number: 20030151089Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: ApplicationFiled: December 19, 2002Publication date: August 14, 2003Inventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland