Patents by Inventor Joe W. McPherson

Joe W. McPherson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit using a back gate voltage for burn-in operations
    Patent number: 5963779
    Abstract: Integrated circuit architectures and methods of operation are provided that allow for the connection of a negative back-gate bias voltage to substrate contacts 24, 90, and 56 during burn-in operations. Accordingly, latch up conditions are prevented during burn-in operations when a circuit is especially vulnerable to such conditions and a grounded substrate is provided to allow for the most efficient operation of the circuit during normal conditions.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: October 5, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Anthony W. Leigh, Joe W. McPherson, Kenan J. Dickerson
  • Polycide process for integrated circuits
    Patent number: 4816425
    Abstract: A process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.
    Type: Grant
    Filed: April 6, 1987
    Date of Patent: March 28, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Joe W. McPherson
  • Polycide electrodes for integrated circuits
    Patent number: 4700215
    Abstract: A semiconductor integrated circuit has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.
    Type: Grant
    Filed: November 19, 1981
    Date of Patent: October 13, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Joe W. McPherson
  • Thermally matched mounting substrate
    Patent number: 4650922
    Abstract: A mounting substrate (10) is formed from a platelet of graphite (22) conformally coated with a layer of silicon carbide (24). A layer of silicon dioxide (25) is disposed thereon and a chip (16) mounted onto the substrate (10). The silicon carbide has a thermal expansion coefficient that is essentially equal to silicon in addition to a high thermal conductivity.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: March 17, 1987
    Assignee: Texas Instruments Incorporated
    Inventor: Joe W. McPherson