Abstract: A computer system that functions as a cordless telephone base unit is disclosed. The computer system includes a cordless telephone device that can be operative through the computer system. The cordless telephone device can function as a cordless telephone base unit with the help of an external antenna that can be attached to the computer system housing. The cordless telephone device may, for example, include a cordless telephone card installed in one of a plurality of connector slots on the computer system motherboard. The cordless telephone device is coupled to a sound device, which may be a computer sound card and may also be installed on the computer system motherboard. The cordless telephone device comprises a cordless telephone base unit, a microphone output and a speaker input to allow the cordless telephone device to be coupled to the sound device in the computer system.

Abstract: An electrical receptacle that provides dual-mode electric power through two separate sockets. The electrical receptacle includes a first socket configured to supply AC electric current at a high voltage (such as 120V or 240V AC) and a second socket configured to supply DC current at a low voltage current (such as 4V, 6V, or 12V DC). In one embodiment, the receptacle receives the high-voltage AC from electrical wiring in a building and generates the low-voltage DC. This embodiment of the receptacle has input terminals for receiving AC, mounting hardware, an AC-to-DC converter, and one or more DC output sockets. The receptacle may also have a standard AC output socket. The receptacle may be used to provide direct current at several different voltage levels. The different voltages may be accessed simultaneously through several different DC sockets. Alternatively or in combination, one or more switches may be used to select the voltage level delivered by individual sockets or groups of sockets.

Abstract: An intermediate frequency gain and rectifying stage for an IF system is implemented with a high swing folded-casecode structure terminated into a current-mirror load. The signal-path outputs are derived from the current-mirror loads, and the rectification and current-limiting RSSI functions are performed with two additional constant-current sources and two additional current-mirror loads. One load current from one leg or current path of the signal-path gain-stage is mirrored into a constant-current source and a second current-mirror structure. A second leg or current path of the signal-path gain-stage is likewise mirrored into yet another constant-current source and another current-mirror structure. When the input signal is not present, the load currents in the signal-path gain-stage are equal and the rectified output signal on an output node IOUT is constant or set to zero.

Abstract: An IF receiver system includes an IF signal path formed by an IF amplifier section, a bandpass filter, and a limiter section. An RSSI (Receive Signal Strength Indicator) circuit is coupled to the IF amplifier section and the limiter section and generates an RSSI output signal which varies linearly with logrithmic changes in input power. A storage unit is coupled to the RSSI circuit and is configured to store a value which controls current limiting associated with the RSSI circuit. In one specific implementation, the limiter section includes a plurality of serially coupled limiter stages. The RSSI circuit includes a plurality of rectifying stages, wherein a separate rectifying stage is coupled to an input of a corresponding limiter stage. An additional rectifying stage is coupled to an output of a last of the limiting stages. The value within the storage unit controls the extent of current limiting associated with the additional rectifying stage.

Abstract: An I/O port interrupt mechanism includes a source register connected to the port for reporting sources of interrupts arising within the port, an interrupt mask register connected to the source register and operable to configure the I/O port for generation of interrupts, and an interrupt controller connected to the output of the source register and operable to hold off interrupts arising within the I/O port.

Abstract: A transmitter for converting a binary digital signal into a pseudo-ternary signal at first and second output nodes (40, 41) to form differential output voltages includes a current source amplifier circuit (10), a first voltage source amplifier circuit (12) and a second voltage source amplifier circuit (14). The current source amplifier circuit (10) is responsive to a reference current for generating a first drive current and a second drive current. The first voltage source amplifier circuit (12) is responsive to a reference voltage, a first digital control signal, a second digital control signal and the first drive current for driving the first output node (40) to the reference voltage when the second digital control signal is at a high logic level and for driving the first output node (40) to a ground potential when the first digital control signal is at a high logic level.

Abstract: A digital-to-analog converter network for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder array (8a), a reference current source (IREF), a plurality of switches (S1, S2, . . . S9) associated with ladder sections of the ladder array (8a), and an operational amplifier (14). An equalization circuit (17) is operatively coupled to the inverting input of the operational amplifier (14) for selectively switching in a code-dependent impedance so that the effective output impedance of the ladder array (8a) remains substantially constant with binary codes of the digital input signal.

Abstract: A transmitter for converting a binary digital signal into a pseudo-ternary signal. The transmitter has been designed so as to overcome the problem of line clamping during a power-down condition, provides a current limiting function, and reduces the ringing problem associated with driving an inductive load with a high impedance source.

Abstract: A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.

Abstract: A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

Abstract: An A/D system having a capacitive DAC is provided with a circuit for accurately testing the functionality of the A/D system. An accurate reference voltage which is associated with A/D systems is utilized directly by selectively coupling the accurate reference voltage to predetermined ones of a plurality of rank ordered capacitors forming a binarily weighted DAC via a plurality of switches. After charging the predetermined capacitors, an effective test voltage results which is then coupled by the switches to successive approximation circuitry associated with the A/D system. A resulting digital output code may be compared with the weighted analog value of the switched reference voltage to test whether the circuitry of the A/D system is functioning properly.

Abstract: A fully differential gain stage having high gain and common-mode feedback is provided with minimal circuitry. Differential input transistors adapted to receive differential input voltages are coupled to load transistors. During a first time period, the gain stage is placed in unity gain and the load transistors are configured as diodes. Charge storage devices are charged during the first time period with a charge which is proportional to both the current of a current supply and the physical dimensions of the load transistors. During a second time period, the charge storage devices provide a bias voltage to the load transistors which maintains the common-mode output voltage at a predetermined value. During the second time period, the gain stage is configured for high gain operation.

Abstract: A capacitive digital to analog converter which can be trimmed to obtain precise capacitor matching is provided. The trimming method may be utilized with a weighted capacitive D/A converter having a scaling capacitor and an ordered plurality of capacitors for developing an analog output signal as a function of a digital input code. A compensation portion is coupled to at least a predetermined one of the capacitors for selectively changing the effective capacitive value of the predetermined capacitor.

Abstract: A fully differential operational amplifier is provided having a common-mode feedback portion which accurately sets the common-mode output voltage at a predetermined value. The feedback portion utilizes a pair of parallel transistors which source a combined current which is used to provide a common-mode control voltage relative to a reference common-mode current. The common-mode control voltage controls load devices of the operational amplifier in a manner such that a differential output voltage remains centered about the predetermined common-mode output voltage.

Abstract: An on chip voltage monitor is provided for an integrated circuit having an analog to digital converter. In one form, the threshold voltage of a plurality of diode-connected test transistors is monitored by selectively positioning the transistors on an integrated circuit die. For each test transistor, a current source in response to a control circuit is selectively coupled thereto for sourcing predetermined amounts of current. The analog to digital converter in response to the control circuit is selectively coupled to the test transistor to measure the voltage across the test transistor. From this data, an accurate approximation of the threshold voltage may be made. Other voltages which are not easily externally measureable may be coupled to the on chip digital to analog converter for easy and accurate measurement.

Abstract: A switched capacitor comparator having two or more stages of differential input operational amplifiers utilizing sequentially switched feedback portions and feedback capacitors is provided. The use of feedback capacitors in a sequentially switched comparator provides accurate gain and stability. To further reduce offset voltage errors, a solid state transmission gate having a low "on" resistance is disclosed. A transmission gate having capacitors for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate is provided to compensate parasitic capacitance effects. When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

Abstract: A solid state transmission gate having a low "on" resistance utilizes capacitive devices for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate to compensate for parasitic capacitance effects. When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.

Abstract: A hysteresis circuit is added to a differential comparator to provide a predetermined bias current from one of two input transistors connected in a differential configuration. A current mirror structure is used to accurately determine the amount of current which is shunted when the output of the comparator is in a predetermined state.