Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Abstract: A coaxial wire interconnect architecture and associated methods are described. In one example, the coaxial wire interconnect architecture is used in a test socket interconnect array. Flexible bends are formed in one or more of the coaxial wire interconnects to provide compliant connections to an electronic device during testing.

Abstract: A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

Abstract: An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

Abstract: Disclosed embodiments include composite compliant pillars in a micro-structure array that extend at a non-orthogonal angle from a heat-sink base. The array is deployed against an integrated-circuit device package to deflect the composite compliant pillar array under conditions where heat-transfer performance is agnostic to dynamic non-planarity of the integrated-circuit device package.

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

Abstract: A coaxial wire interconnect architecture and associated methods are described. In one example, the coaxial wire interconnect architecture is used in a test socket interconnect array. Flexible bends are formed in one or more of the coaxial wire interconnects to provide compliant connections to an electronic device during testing.

Abstract: A shielded interconnect array and associated methods are described. Examples of the shielded interconnect array include socket connections that include conductive members with flexible bends. In examples shown, corresponding grounded conductive members with flexible bends are located adjacent to other conductive members with flexible bends to provide shielding.

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.