Patents by Inventor Joe Walczyk

Joe Walczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210088554
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 10935573
    Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Joe Walczyk, Pooya Tadayon
  • Publication number: 20200411408
    Abstract: Disclosed embodiments include composite compliant pillars in a micro-structure array that extend at a non-orthogonal angle from a heat-sink base. The array is deployed against an integrated-circuit device package to deflect the composite compliant pillar array under conditions where heat-transfer performance is agnostic to dynamic non-planarity of the integrated-circuit device package.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Joe Walczyk, Pooya Tadayon, Michael Rutigliano, Chandra M. Jha, Zhimin Wan
  • Patent number: 10877068
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20200141979
    Abstract: A coaxial wire interconnect architecture and associated methods are described. In one example, the coaxial wire interconnect architecture is used in a test socket interconnect array. Flexible bends are formed in one or more of the coaxial wire interconnects to provide compliant connections to an electronic device during testing.
    Type: Application
    Filed: March 31, 2017
    Publication date: May 7, 2020
    Inventors: Ronald Michael Kirby, Erkan Acar, Joe Walczyk, Youngseok Oh, Justin M Huttula, Mohanraj Prabhugoud
  • Patent number: 10644458
    Abstract: A shielded interconnect array and associated methods are described. Examples of the shielded interconnect array include socket connections that include conductive members with flexible bends. In examples shown, corresponding grounded conductive members with flexible bends are located adjacent to other conductive members with flexible bends to provide shielding.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Youngseok Oh, Justin M Huttula, Mohanraj Prabhugoud, Ronald Kirby, Joe Walczyk, Erkan Acar
  • Publication number: 20200103440
    Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Joe Walczyk, Pooya Tadayon
  • Patent number: 10566263
    Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Joe Walczyk, John C. Johnson
  • Publication number: 20200025801
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 10488438
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20190212366
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 11, 2019
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20190204358
    Abstract: An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 4, 2019
    Inventors: Paul Diglio, Joe Walczyk
  • Publication number: 20190203370
    Abstract: A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Joe Walczyk, Pooya Tadayon, Andrew Hoitink, Tanner Schulz
  • Patent number: 10338099
    Abstract: A socket assembly for a microelectronic device can include a body and a plurality of arm. The body can include a central socket configured to receive a microelectronic device therein. The plurality of arms can each be adjacent to the central socket, where each of the plurality of arms can be rotatably coupled to the body and each of the plurality of arms can be translatable relative to the body to move between an open position and a closed position. The arms can retain a microelectronic device within the central socket when the arms are in the closed position.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Christopher Del Barga, Joe Walczyk, Ronald Michael Kirby
  • Publication number: 20190096785
    Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Joe Walczyk, John C. Johnson
  • Publication number: 20180364279
    Abstract: A socket assembly for a microelectronic device can include a body and a plurality of arm. The body can include a central socket configured to receive a microelectronic device therein. The plurality of arms can each be adjacent to the central socket, where each of the plurality of arms can be rotatably coupled to the body and each of the plurality of arms can be translatable relative to the body to move between an open position and a closed position. The arms can retain a microelectronic device within the central socket when the arms are in the closed position.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Christopher Del Barga, Joe Walczyk, Ronald Michael Kirby
  • Publication number: 20180287305
    Abstract: A shielded interconnect array and associated methods are described. Examples of the shielded interconnect array include socket connections that include conductive members with flexible bends. In examples shown, corresponding grounded conductive members with flexible bends are located adjacent to other conductive members with flexible bends to provide shielding.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Youngseok Oh, Justin M. Huttula, Mohanraj Probhugoud, Ronald Kirby, Joe Walczyk, Erkan Acar
  • Publication number: 20170273176
    Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Youngseok Oh, Joe Walczyk
  • Patent number: 9674943
    Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Youngseok Oh, Joe Walczyk
  • Patent number: 9046569
    Abstract: Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments, an apparatus comprises a probe head assembly configured to hold one or more probes that are adapted to provide electrical contact with an integrated circuit device under test (DUT), a DUT chuck adapted to hold the DUT for contact with the probes, a seal arranged between the probe head assembly and the DUT chuck to form a chamber when the seal is in contact with the probe head assembly and the DUT chuck, and a first port and a second port arranged to provide fluid flow into and fluid flow out of the chamber.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Ronald Kirby, James G. Maveety, Joe Walczyk