Patents by Inventor Joe Zelayeta

Joe Zelayeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6078502
    Abstract: Electronic system utilizing semiconductor devices having heat dissipating leadframes are provided by using materials, such as copper, which exhibit good thermal and electrical conductivity, and arranging the lead fingers of the leadframe in a configuration which provides good thermal coupling with the surface of a semiconductor die. Micro-bump bonding techniques are employed to provide additional thermal coupling at the electrical connection point of the leadframe fingers to the die. Leadframe fingers exhibiting a high aspect ratio (height:width) are described. Leadframe fingers extending substantially beyond interior bond pads are described.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: June 20, 2000
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5666189
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: September 9, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5643830
    Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: July 1, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5591564
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of Gamma-radiation. A continuous stream of such radiation, such as provided by a pellet of Cobalt-60, is collimated into a fine beam by a tapered collimator, and is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The fine, collimated beam converts points in a gamma-radiation-sensitive layer on a semiconductor wafer. By moving the wafer relative to the beam (or vice-versa), patterns are created in the layer of radiation-sensitive layer for further processing a layer underlying the radiation-sensitive layer.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: January 7, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5572562
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a source of X-ray radiation. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with a patterned opaque material on a surface of a substrate thereof. The substrate is formed of beryllium, which is robust and has a thermal coefficient of expansion closely conforming to that of common image mask carriers. Further, a wide variety of opaqueing materials adhere well to the beryllium substrate, and the substrate is relatively insensitive to moisture. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: November 5, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5567655
    Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping (laying out) the bond pads in two parallel rows, approximately centered about a central axis of the die. Further, the bond pads of one row are axially offset from the bond pads of the other row, thereby forming a two-row zig-zag linear configuration of bond pads. The "axis" is a line preferably passing through a thermal centroid of the die. By keeping the bond pad layout close to the axis, lateral thermally-induced displacements of the bond pads relative to the axis can be minimized and controlled. Longitudinal (axial) displacements of the bond pads are accommodated by flexing, rather than compression, of conductive lines (such as leadframe fingers) connecting to the bond pads and entering the die perpendicular to the axis.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 22, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5567570
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of Gamma-radiation. A continuous stream of such radiation, such as provided by a pellet of Cobalt-60, is collimated into a fine beam by a tapered collimator, and is gaged on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The fine, collimated beam converts points in a gamma-radiation-sensitive layer on a semiconductor wafer. By moving the wafer relative to the beam (or vice-versa), patterns are created in the layer of radiation-sensitive layer for further processing a layer underlying the radiation-sensitive layer.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 22, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5557066
    Abstract: Plastic (or resinous) materials used to package (or support) electronic devices typically have thermal coefficients of expansion exceeding that of the device to be packaged. A "loading" material (agent) having a coefficient of expansion significantly less than the "base" plastic material (molding compound), less than that of the die, and preferably zero or negative over a temperature range of interest, is mixed with the "base" plastic material to produce a plastic molding compound with a lower overall thermal coefficient of expansion. Titanium dioxide, zirconium oxide and silicon are discussed as loading agents. The loading material is mixed into the plastic molding compound in sufficient quantity to ensure that the resulting mixture exhibits an overall thermal coefficient of expansion that is more closely matched to that of the electronic device.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: September 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5554484
    Abstract: Fine, sub-micron line features and patterns are created in a radiation sensitive resist layer on a semiconductor wafer by a beam of short wavelength gamma rays. The resist layer includes photoresist which is substantially chemically inactive in response to the gamma rays. The photoresist is either doped or covered with a material that absorbs gamma rays and in response emits secondary radiation of a different wavelength, preferably photons, that is actinic with respect to the photoresist. The resist layer enables using radiation sources having better resolving ability than conventional photolithographic sources to perform near-field and direct-write lithography.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: September 10, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5512395
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: April 30, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5485243
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: January 16, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5478698
    Abstract: A technique is describe for effecting very-high resolution semiconductor lithography using direct-write afocal electron-beam exposure of a sensitized wafer. A positioning mechanism and needle-like probe similar to those used in scanning-tunneling microscopy are used in conjunction with a controllable electron field emission source to produce a near-field electron beam capable of exposing an electron-beam sensitive resist on a wafer surface. Conventional e-beam resists are used. The technique can be used in conjunction with scanning-tunneling-like operation of the apparatus to record the appearance and nature of the wafer surface, thereby providing information about the location of underlying features. This location information can be used to assist in aligning the exposure patterns to existing structures in the semiconductor wafer.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: December 26, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5453583
    Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: September 26, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5384487
    Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: January 24, 1995
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5374974
    Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A continuous stream of such radiation is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The distortable-surface device is a surface acoustic wave device, a magnetostrictive device, or the like. The beam-blocking device is a beam stop, such as a knife edge, an aperture, or the like. The distortable-surface device can be selectively caused to reflect an incident beam of radiation past or into the beam-blocking device. In this manner, a continuous stream of radiation, such as from a pellet of Cobalt-60, can be quickly and precisely gated on and off to impact and to not-impact the semiconductor wafer, respectively. By moving either of the reflected beam or the semiconductor wafer, line features can be created in the sensitized layer on the semiconductor wafer.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 20, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5345310
    Abstract: Techniques for identifying and determining the orientation, magnitude, and direction of slip plane dislocations transecting semiconductor dies are described, whereby a four point alignment pattern is examined for "squareness" and size integrity. Lack of squareness or significant change in apparent size of various aspects of the alignment pattern indicate slip-plane dislocations. The magnitude, orientation and direction of the dislocations are determined geometrically from measurement of the alignment pattern. Various other aspects of the invention are directed to optimal alignment of a photolithographic mask to a die which has experienced a slip-plane dislocation, and to discrimination between slip-plane dislocation and die-site rotation.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: September 6, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta