Abstract: A medical imaging and/or radiotherapy apparatus incorporates a display for projecting a visible image to a patient lying on a patient table. A projector that projects the visible image moves in tandem with the patient table, so that it appears relatively motionless to the patient. In exemplary embodiments, the projector projects the visible image within a patient tunnel of the medical apparatus, including in some embodiments, an extended field of view medical imaging apparatus. In other exemplary embodiments, the projector projects the visible image on a screen above the patient table of a tunnel-less medical apparatus. The projector remains outside the imaging line of response of detectors within the imaging field or outside of the radiotherapy beam zone, to avoid potential degradation of the captured diagnostic image or degradation of the radiotherapy beam.

Abstract: A medical imaging and/or radiotherapy apparatus incorporates a display for projecting a visible image to a patient lying on a patient table. A projector that projects the visible image moves in tandem with the patient table, so that it appears relatively motionless to the patient. In exemplary embodiments, the projector projects the visible image within a patient tunnel of the medical apparatus, including in some embodiments, an extended field of view medical imaging apparatus. In other exemplary embodiments, the projector projects the visible image on a screen above the patient table of a tunnel-less medical apparatus. The projector remains outside the imaging line of response of detectors within the imaging field or outside of the radiotherapy beam zone, to avoid potential degradation of the captured diagnostic image or degradation of the radiotherapy beam.

Abstract: A PET system includes an improved image reconstruction algorithm based on an improved modeling of the point-spread function. PET time of flight data is used to obtain a mean emitting point and a time of flight probability function. This information is then used to model the point-spread function. The time of flight probability function and the detector response function are used to define a probability volume for a given line of response, which is then used in the reconstruction of the image.

Abstract: A PET system includes an improved image reconstruction algorithm based on an improved modeling of the point-spread function. PET time of flight data is used to obtain a mean emitting point and a time of flight probability function. This information is then used to model the point-spread function. The time of flight probability function and the detector response function are used to define a probability volume for a given line of response, which is then used in the reconstruction of the image.

Abstract: A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.

Abstract: There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS storage capacitor. The word lines are coupled to their respective memory cells at the gate of the field-effect transistor therein, while the bit lines are coupled to their respective memory cells at the drain of the field-effect transistor. The bit lines are organized into pairs of adjacent polysilicon lines that are coupled to all the memory cells on both sides of the bit lines in an alternating configuration. The word lines are coupled to alternating pairs of cells on opposite sides of the word lines.

Abstract: A warning device is responsive to the failure of an electric power supply for activation to a warning mode. The warning device includes an arm pivotally mounted to a frame member and latched by an electromagnet in a non-warning mode. In the non-warning mode, a collapsible warning sign carrier is enclosed within an enclosure formed by the frame and the arm. When the supply of power is interrupted, the electromagnet releases the arm so that the arm pivots to a warning position.

Abstract: A method and apparatus for eliminating the effects of ionizing radiation on computer system are disclosed in which two redundant storage units are alternately addressed and updated in rapid succession so that each storage unit alternately carries information unaffected by the radiation. After the radiation has ceased, this unaffected unit is located and its information read back into the computer system.

Abstract: A semiconductor memory is comprised of a semiconductor substrate having first and second spaced apart arrays of memory cells disposed thereon. A plurality of first pairs of bit lines couple to the cells of the first array, and a corresponding plurality of second pairs of bit lines couple to the cells of the second array. Disposed between each first pair and corresponding second pair of bit lines is one X sense amplifier. This amplifier includes a set node selectively coupled to one bit line of the first pair and to one bit line of the second pair, and a reset node selectively coupled to the opposite bit lines of the first and second pair for selectively sensing charge on the four bit lines.

Abstract: An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps.

Abstract: An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps.

Abstract: In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells.