Abstract: A memory mapper for an emulation system suitable for a microprocessor-based system for any size microprocessor is disclosed which uses function code comparators, range comparators, and offset values for individual mapping definitions, thereby providing faster mapping of emulation memory with higher resolution and flexibility in making changes. A single mapper cell is used for implementing each separate mapping definition. The function code comparator for the mapper cell defines the type of memory, the range comparator defines the section of memory covered by the mapper definition, and a translator is used to translate the original address to a translated address by adding an offset to the original address. Original addresses which do not match any mapper cell definitions are mapped according to a default definition.

Abstract: A timing or logic state analyzer automatically places marks into a captured trace measurement. The definition of each mark may include an associated collection of logical conditions in the captured data. Once the trace measurement is complete the analyzer searches through the captured data, locates where any defined conditions occur and adds the associated mark into the corresponding location of the reconstructed waveforms or trace list. Certain marks may be placed at each occurrence of a specified event in the trace, while other marks are restricted to placement at the first occurrence. Marks can be defined in terms of prior and subsequent occurrence of other marks, or of other features in the trace such as a user positionable cursor or a stated sample number. The definition of the marks need not be specified prior to the trace measurement, and an existing trace measurement already captured can be examined and re-examined with different marking schemes without repeating the overall trace measurement.

Abstract: A timing analyzer incorporates pattern transition and pattern duration triggering. A transition detector detects transitions into or out of selected patterns occurring among the inputs of the analyzer. A time duration comparator compares a selected logical sense of the pattern against a variable duration reference. The outputs of the transition detector and of the time duration comparator are combined with logic circuits to produce a qualified trigger signal indicative of a simple transition into or out of a selected pattern, duration of the pattern longer than some reference, or shorter than that reference.