Patents by Inventor Joel B. deNeuf

Joel B. deNeuf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5430605
    Abstract: A composite multilayer capacitive device (10) has a series resistance. A capacitor body (14) is defined by a plurality of interleaved first and second ceramic layers (21, 23) having respective first and second electrode patterns (22, 24) which establish a selectable capacitance. In a first embodiment, the first and second electrode patterns (22, 24) are generally rectangular with protruding interconnect elements (27, 28). In a second embodiment, the first and second electrode patterns (62, 64) are similar to those in the first embodiment, except that the second electrode pattern (64) has no interconnect element and is elongated in order to directly contact the second termination (18). In a third embodiment, the first and second electrode patterns (82, 84) are generally rectangular with first, second, and third protruding interconnect elements (87a-87c, 88a-88c).
    Type: Grant
    Filed: July 7, 1993
    Date of Patent: July 4, 1995
    Assignee: Murata Erie North America, Inc.
    Inventors: Joel B. deNeuf, Bruce E. Helms
  • Patent number: 5347423
    Abstract: In a first embodiment, a trimmable composite multilayer capacitor (10) is fabricated with a novel process so that the capacitor (10) exhibits a high quality factor Q and is capable of efficient and accurate functional trimming over a wide range while in a circuit. The capacitor (10) comprises a capacitor body (12) defined by a plurality of interleaved first and second electrodes (14, 16) spaced apart by dielectric material. The plurality establishes a fixed capacitance value. The plurality is co-fired at a first temperature. A trimmable outermost electrode (14') is disposed on the exterior of the capacitor body (12) and is capable of depletion for particularly selecting the overall capacitance value of the capacitor (10). The trimmable outermost electrode is sintered on the capacitor body (12) at a second temperature which is less than the first temperature. Finally, first and second terminations (24, 26) are positioned at the ends of the capacitor body (12).
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: September 13, 1994
    Assignee: Murata Erie North America, Inc.
    Inventors: Joel B. deNeuf, Bruce E. Helms, Delmont L. Billotte
  • Patent number: 5345361
    Abstract: A shorted trimmable composite multilayer capacitor (10) is initially shorted, but can be easily and efficiently unshorted and then functional trimmed while in a circuit. The capacitor (10) has a capacitor body (12) defined by a plurality of interleaved first and second electrodes (14, 16) spaced apart by ceramic. A trimmable outermost electrode (14') is situated on the capacitor body (12) and is capable of depletion by trimming for particularly selecting a capacitance associated with the capacitor (10). First and second terminations (24, 26) are disposed at first and second ends of the capacitor body (12) for connecting the capacitor (10) to a circuit. The first termination (24) is connected to the first electrodes (14), while the second termination is connected to the second electrode (16). Importantly, an interconnect bar (15) is disposed on the capacitor body (12) for connecting the outermost electrode (14') to the second termination (26) to thereby short the first and second terminations (24, 26).
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: September 6, 1994
    Assignee: Murata Erie North America, Inc.
    Inventors: Delmont L. Billotte, Joel B. deNeuf, Bruce E. Helms
  • Patent number: 5227951
    Abstract: A composite multilayer capacitive device (10) has an in series resistance. A capacitor body (14) is defined by a plurality of interleaved first and second ceramic layers (21, 23) having respective first and second electrode patterns (22, 24) which establish a selectable capacitance. A first termination (16) is disposed at a first end of the capacitor body (14) and is connected to the first electrode patterns (22) of the first ceramic layers (21). A second termination (18) is disposed at a second end of the capacitor body (14) and is connected to the second electrode patterns (24) of the second ceramic layers (23) through a lateral resistive layer (12) which is transversely engaged with the second electrode patterns (24) of the second ceramic layers (23) and with the second termination (18). As a result, the lateral resistive layer (12) serves as an in series resistance between the first and second terminations (16, 18).
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: July 13, 1993
    Assignee: Murata Erie North America, Inc.
    Inventors: Joel B. deNeuf, Bruce E. Helms