Abstract: A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell groups organized along a first dimension, keeping track of failures seen in each of the respective memory cell groups in the first set, and keeping track of and designating as a must-repair memory cell group any memory cell group whose respective number of failures equals or exceeds a first maximum failure threshold.

Abstract: Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.

Abstract: Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.

Abstract: A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell groups organized along a first dimension, keeping track of failures seen in each of the respective memory cell groups in the first set, and keeping track of and designating as a must-repair memory cell group any memory cell group whose respective number of failures equals or exceeds a first maximum failure threshold.

Abstract: A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs.

Abstract: An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

Abstract: A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs.

Abstract: A collision detection method and apparatus that detects the likelihood of a collision with an address of data previously retrieved from a two dimensional memory array, such as a memory array suitable for use as the frame buffer memory within a graphics display sub-system of a computer system. The collision detection system can also view the memory as having only one dimension to detect the likelihood of a collision with higher or lower accesses relative to a current access.