Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer, and forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck. The gate foot has a first width, and the gate neck has a second width that is wider than the first width. The gate neck extends for a length over the dielectric passivation layer on both sides of the first opening. The gate head has a third width wider than the second width of the gate neck.

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said first component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip top surface; a first conductor connecting said wafer contact pad and said component contact pad.

Abstract: A self-aligned GaN FinFET device and a method of fabricating the same are disclosed. This self-aligned process helps to fabricate GaN FinFET devices in a scalable manner. This work transforms the T-gate process to incorporate fins to further improve pinch-off and decrease leakage currents on highly scaled GaN HEMT structures. The GaN FinFET structure will also allow for integration of normally-off devices with normally-on devices by varying the fin width. The FinFET improvement combines the fin structure consisting of various fin pitches and widths, gate dielectric, self-aligned gate design, ultra-low ohmic contacts, and vertically scaled epitaxy into a single scalable process.

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

Abstract: An integrated component having a metallic interlocking structure; the integrated component comprising an integrated circuit integrated in a substrate having a top surface; the integrated circuit comprising a first conducting line; and a first metallic interlocking structure comprising a first array of free-standing metallic columns formed on said top surface and electrically connected to said first conducting line.

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by an attachment material attaching at least one wall of the through-wafer cavity to at least one of the component chip bottom surface and a component chip side surface; said component chip comprising at least one component contact pad on said component chip top substrate; a first conductor connecting said wafer contact pad and said component contact pad.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.