Abstract: The present disclosure provides a method for communicating data between a slave device and a master device according to a communication protocol. An example includes the data being recorded in a memory belonging to the slave device, the method comprising a generation by the master device of a command provided by the communication protocol, and use of a field of the command in order to select an indirection register belonging to the slave device and containing an address of a region of the memory including the data.

Abstract: The present invention relates to a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and circuitry for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.

Abstract: A device for the digital performance of a binary division according to a non-restoring type of division method chiefly comprises a circuit for the detection of null partial remainders during the division. Advantageously, combinational circuits are designed to compute a correction bit to correct the quotient in a single instruction. Finally, there is advantageously provided a circuit for the computation, at each division step, of the complemented quotient bit for the next division step and a multiplexer for the introduction, at the next step, of the reverse of this complemented quotient bit on the least significant position of the quotient. Application to signal processors.

Abstract: A computation device comprising an arithmetic and logic unit with an accumulation register and a condition register to store information bits of a current operation in the arithmetic and logic unit comprises circuits to determine which one of two operands applied as inputs to the arithmetic and is the smallest or the greatest and comprises circuits to write the smallest or the greatest operand thus determined in the associated accumulator register.

Abstract: An arithmetic and logic computation device having an arithmetic and logic unit with a shifter on at least one input. The computation device, which includes a multiplier, propagates a carry and applies a carry to the multiplier to carry out double precision multiply and multiply-accumulate operations.

Abstract: A digital operand formatting stage that includes a first inverting means, a second inverting means having an input that is connected to the input of the first inverting means, and a third inverting means having an input that is connected to the output of the second inverting means, and an output that is connected to the output of the first inverting means. A first and third switching means are controlled by a first control signal and provide electrical connections between a positive voltage supply and the respective supply side of the first and third inverting means. A second and fourth switching means are controlled by a second control signal and provide electrical connections between a negative voltage supply and the respective ground sides of the first and third inverting means.