Abstract: A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

Abstract: A method and apparatus for generating floating point condition codes by using the data type of a result operand, rather than a magnitude relationship between two operands. The condition codes may then be combined to generate relations useful for identifying conditions for conditional branches or traps.

Abstract: A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The processor thus proceeds to the next instruction as if the power-down instruction were a "no-operation" instruction.

Abstract: A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set.

Abstract: A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.