Abstract: Disclosed herein are systems, devices, and methods for retracting tissue and removing surgical smoke using a smoke evacuation conduit positioned on or within an internal surface of the retractor blade such that the conduit does not protrude onto the external surface of the blade, along with a smoke intake port on or flush with the exterior surface of the blade and set back from the tip to minimize tissue aspiration. The systems and devices allow for the channeling of surgical smoke away from the surgical site while avoiding occlusion of the surgeon's field of view and preserving the surgeon's freedom of motion.

Abstract: A valve actuator includes a valve body, a valve member comprising a shaft, and a piston connected to the shaft, with the valve member being movable by operation of the piston. The valve body comprises a valve chamber that provides fluid communication between an inlet passage and an outlet passage. The shaft is disposed in and extends through a sealed chamber, the sealed chamber being sealed at one end from the valve chamber and at another end from a piston chamber, and a vent that extends from the sealed chamber to an external surface, wherein the shaft extends axially in both directions past sealed ends of the sealed chamber.

Abstract: The present application relates to valve and actuator assemblies. The valve actuator assemblies may include a capless valve actuating arrangement, include a replaceable passage defining member that includes seal members, include a valve member that is assembled in a valve chamber from an end of the valve body that is opposite an end that a piston is assembled in, and/or include a valve member that may be rotated in a valve body without affecting the ability of the valve member to perform its sealing functions.

Abstract: The present application relates to valve and actuator assemblies. The valve actuator assemblies may include a capless valve actuating arrangement, include a replaceable passage defining member that includes seal members, include a valve member that is assembled in a valve chamber from an end of the valve body that is opposite an end that a piston is assembled in, and/or include a valve member that may be rotated in a valve body without affecting the ability of the valve member to perform its sealing functions.

Abstract: The present disclosure relates generally to semiconductor devices and related methods of operation. A semiconductor device is disclosed that comprises at least one cipher interface (126, 128) to a plurality of different cipher hardware modules (112, 114, 116) and central mode control logic (130-138, 106) responsive to the at least one cipher interface (126, 128). The central mode control logic (130-138, 106) is configured to provide a cipher operation in accordance with a selected cipher mode (104) in connection with at least one of the plurality of different cipher hardware modules (112, 114, 116).

Abstract: The present application relates to valve and actuator assemblies. The valve actuator assemblies may include a capless valve actuating arrangement, include a replaceable passage defining member that includes seal members, include a valve member that is assembled in a valve chamber from an end of the valve body that is opposite an end that a piston is assembled in, and/or include a valve member that may be rotated in a valve body without affecting the ability of the valve member to perform its sealing functions.

Abstract: The present application relates to valve and actuator assemblies. The valve actuator assemblies may include a capless valve actuating arrangement, include a replaceable passage defining member that includes seal members, include a valve member that is assembled in a valve chamber from an end of the valve body that is opposite an end that a piston is assembled in, and/or include a valve member that may be rotated in a valve body without affecting the ability of the valve member to perform its sealing functions.

Abstract: Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.

Abstract: The present disclosure relates generally to semiconductor devices and related methods of operation. A semiconductor device is disclosed that comprises at least one cipher interface (126, 128) to a plurality of different cipher hardware modules (112, 114, 116) and central mode control logic (130-138, 106) responsive to the at least one cipher interface (126, 128). The central mode control logic (130-138, 106) is configured to provide a cipher operation in accordance with a selected cipher mode (104) in connection with at least one of the plurality of different cipher hardware modules (112, 114, 116).

Abstract: A method of performing encryption and decryption includes implementing a block cipher algorithm, generating encryption and decryption round keys for an accelerator module, and implementing the accelerator module using shared logic for one or more round key sizes, wherein the decryption uses a stored expanded key word to initialize subsequent block decryptions. The block cipher algorithm can be the Rijndael algorithm. Only a first block decryption requires expansion overhead. All subsequent block decryptions utilize a prior key to initialize a key expansion engine for a plurality of subsequent blocks. The subsequent block decryptions are performed at a same rate as block encryptions. An apparatus includes a plurality of logic gates configured to reuse expanded round keys from a prior decryption round, the logic gates complete one round of data decryption per clock cycle after an initial round of data decryption, and a plurality of decoders configured to convert the decrypted data to usable data.

Abstract: In a speech recognition system disclosed herein, acoustic speech waveforms are initially analyzed to obtain, at successive sample times, digital frames of speech information. This initial analysis may, for example, be performed by multi-channel filtering or linear predictive encoding. Stored in the apparatus is a list of representative standard frames, represented by coded indices, together with a table of difference values which represent the vector distances between each standard frame in the list and all other standard frames. For each token (vocabulary) word which is to be recognized, there is stored a sequence of standard frame indices which represent that token word. As each sample frame is generated, a representative standard frame is selected which best represents the sample frame.

Abstract: A very small, very flexible, high-quality, linear predictive vocoder has been implemented with commercially available integrated circuits. This fully digital realization is based on a distributed signal processing architecture employing three commercial Signal Processing Interface (SPI) single chip microcomputers. One SPI implements a linear predictive speech analyzer, a second implements a pitch analyzer while the third implements the excitation generator and synthesizer.