Abstract: A method, system, and product are disclosed for isolating a defect in a memory system by determining in which particular component of the memory system the defect exists. The memory system includes multiple components. The components include a physical memory module, a memory card to which the physical memory module is attached, and a memory controller for controlling the memory card. The memory card includes one or more electrical buffers for driving or detecting the memory signals. The buffers may be used as virtual memory elements. Each component is tested separately in order to identify the defective component with the help of virtual memory system elements. The components are tested by first testing the physical memory module. If the physical memory module passes the test, the memory card is then tested. If the memory card passes its test, the memory controller is tested.

Abstract: An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with other I2C devices and an I2C bus controller that is also on the I2C bus. The switch logic controls a current position of the switches. The I2C device is coupled to the I2C bus utilizing the switches. The switches control whether the main I2C section, the address logic, the switch logic, or a combination of the main I2C section, address logic, and switch logic is currently coupled to I2C bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the I2C device. The I2C device will respond to the address that is stored in its address logic.

Abstract: An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.

Abstract: An apparatus and method for expansion of an inter-IC (I2C) is provided. An expansion processor resides on a primary I2C bus. The expansion processor is coupled to a plurality of I2C sub-buses each of which may host a plurality of I2C devices. Data is transferred between the expansion processor and the plurality of I2C devices via the corresponding sub-bus according to an I2C protocol. Data transfer is in response to a request initiated by a bus master on the primary I2C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which the echos it to the target device.

Abstract: An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.

Abstract: A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

Abstract: A method, system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bud driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch.

Abstract: A key assembly includes a cover disposed over a transducer which is connected to a key acutator/interface disposed between the key transducer and a CPU. A tactile signal generator generates control signals from the CPU to activate the actuator/interface. The actuator/interface provides a signal appropriate to the particular transducer causing it to produce tactile feedback response to the key cover and user's touch. The key assembly may include a larger key cover disposed over a plurality of key transducers whereby the CPU causes texture and fine detail sensations variable over the key cover area by selective, variable actuation of the transducers. The end-user may thereby sense by physical contact with the large key cover electronically generated sensations of irregular surfaces or textures. Tactile profiles either user-specified or automatically invoked by a corresponding application vary the keyboard touch and feel as defined by the selected profile.

Abstract: A data processing system has a reader device adapted to read information residing on a first type of storage article (such as a floppy diskette), and a holder is provided which is substantially identical in size and shape to the first type of storage article, but allows the reader device to read a card which bears machine-readable information, such as a credit card. The holder can have a slot therein for receiving the card, which is aligned within the holder to position a portion of the information medium at an access area of the holder. The machine-readable information can be, for example, encoded on a magnetic strip on the card. The system allows network-based transactions which read from the card as well as write to it.

Abstract: Polling of devices on an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device.