Patents by Inventor Joel Goodrich

Joel Goodrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150027513
    Abstract: A semiconductor substrate and a photovoltaic power module incorporating the semiconductor substrate. The substrate includes one or more bypass diodes formed integrally in the semiconductor substrate, each bypass diode corresponding to a respective one or more photovoltaic cells, and metallised zones being electrically and thermally coupled to the bypass diodes. The substrate enables photovoltaic cells to be placed close together, and has low thermal resistance. Methods of manufacturing the substrate and module are provided.
    Type: Application
    Filed: November 21, 2012
    Publication date: January 29, 2015
    Applicant: Solar Systems Pty Ltd
    Inventors: William Ring, Joel Goodrich, Zhen Mu, Robert Musk
  • Publication number: 20140352759
    Abstract: A photovoltaic power module including a reflector, and methods for manufacturing the reflector. The photovoltaic power module includes a plurality of photovoltaic cells arranged in an array, including a photon source facing surface having a plurality of active areas that convert photons to electrical energy and a plurality of inactive areas that do not convert photons to electrical energy. The reflector covers at least one inactive area of a photon source facing surface, for reflecting photons that would otherwise have fallen on the inactive area onto an active area. The output of the photovoltaic power module may therefore be increased.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 4, 2014
    Applicant: SOLAR SYSTEMS PTY LTD
    Inventors: Brett Barnes, Joel Goodrich, Sam Carter
  • Publication number: 20050269695
    Abstract: A chip-scale package and method of manufacturing a chip-scale package are provided. The chip-scale package includes a mounting portion defined by a plurality of metal layers formed on each of a plurality of semiconductor regions for mounting a device thereto. The mounting portions are formed on a first side of the plurality of semiconductor regions. The chip-scale package further includes a backside metal surface formed on each of a second side of the plurality of semiconductor regions, with the plurality of semiconductor regions providing electrical connection between the mounting portions and the backside metal surfaces.
    Type: Application
    Filed: June 7, 2004
    Publication date: December 8, 2005
    Inventors: James Brogle, Timothy Boles, Joel Goodrich
  • Patent number: 6849879
    Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: February 1, 2005
    Assignee: Teraburst Networks, Inc.
    Inventors: Ross A. La Rue, Jules D. Levine, Daniel Curcio, Timothy Boles, Joel Goodrich, David Hoag, Noyan Kinayman
  • Publication number: 20030075743
    Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 24, 2003
    Inventors: Jules D. Levine, Ross A. La Rue, Daniel Curcio, Timothy Boles, Joel Goodrich, David Hoag, Noyan Kinayman
  • Patent number: 5672282
    Abstract: A process to form integrated circuits comprising silver metal circuits. Deposition techniques such as sputtering, not plating, upon substrates to form such silver metal circuits are common. However in the conventional processes to remove the resist and the metal overlaying the resist, these conventional processes are deleterious to the silver metal. Thereby a new process is provided. This new process entails the metal overlaying the resist of the wafer is initially removed by a high pressure force. The resist, in this new process, is then removed by a benign stripper solution having the temperature of the solution raised to the highest temperature without degrading the stripper solution and said circuit is exposed to said stripper solution for one to five minutes.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: September 30, 1997
    Assignee: The Whitaker Corporation
    Inventors: Percy Chinoy, Joel Goodrich
  • Patent number: 4352948
    Abstract: The invention contemplates a solar-cell construction wherein plural spaced elongate unit cells of an array are formed from a parallel-grooved single wafer or body of substrate material of a first conductivity type, with adjacent sidewalls of adjacent units at each inter-unit groove formation. Both sidewalls at each of a succession of grooves are formed with regions of second conductivity type, and an electrically conductive coating lines each sidewall having a second conductivity type region. A first output-terminal interconnect extends along one margin of the body and has ohmic contact with the coatings of the sidewalls having regions of the second conductivity type. A second output-terminal connection has ohmic contact to the body in a surface region of first conductivity type. Various embodiments are disclosed.
    Type: Grant
    Filed: November 17, 1980
    Date of Patent: October 5, 1982
    Assignee: Massachusetts Institute of Technology
    Inventors: Roy Kaplow, Robert I. Frank, Joel Goodrich