Abstract: An expansion card is provided that allows resources allocated to the expansion card to be shared with a different card. The expansion card comprises a coupling device that couples the expansion card to a data processing system. The expansion card also includes an identifier data structure that when queried by the data processing system, identifies the expansion card as a resource sharing expansion card. The data processing system reallocates one or more resources allocated to the expansion card to a different card coupled to the data processing system.

Abstract: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.

Abstract: Embodiments of the invention relate to efficiently processing read transactions in a shared file system having multiple virtual machines. Each virtual machine in the file system has access to disk storage and local disk cache. At the same time, each virtual machine in the file system has access to remote disk cache of a remote virtual machine. For each read transaction, the local and/or remote disk cache employed for data blocks to support the transaction. Disk storage is employed to support the transaction in the event that the data blocks are not available in the local and/or remote disk cache.

Abstract: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.

Abstract: A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.

Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: In one embodiment, a method is disclosed for allocating memory for a processor unit in a group of processing units. The method can include receiving a memory allocation request where the request can indicate a number of binary segments to be stored. The method can determine if the number indicates a nonstandard allocation, and locate an unallocated memory address based on a multiple of the number if the number indicates a nonstandard allocation. The method can also include locating an unallocated memory address from a pool of memory addresses, where the pool of addresses includes the integer multiples of the binary segments and excludes addresses that are two times the number of binary segments such that the address can be utilized to determine the allocation.

Abstract: Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions.

Abstract: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.

Abstract: A method, system, and computer program product for managing system resources within a data processing system. A resource management moderator (RMM) utility assigns a priority to each application within a group of management applications, facilitated by a RMM protocol. When a request for control of a particular resource is received, the RMM utility compares the priority of the requesting application with the priority of the controlling application. Control of the resource is ultimately given to the management application with the greater priority. If the resource is not under control of an application, control of the resource may be automatically granted to the requester. Additionally, the RMM utility provides support for legacy applications via a “manager of managers” application. The RMM utility registers the “manager of managers” application with the protocol and enables interactions (to reconfigure and enable legacy applications) between the “manager of managers” application and legacy applications.

Abstract: Methods and arrangements to assign locks to threads are discussed. Embodiments include transformations, code, state machines or other logic to assign locks to threads. Embodiments may include setting a window of time at the end of a time slice of a thread. The embodiment may also involve prohibiting the thread from acquiring a lock during the window of time, based upon determining that the thread is within the window of time and determining that the thread does not hold any locks. Other embodiments include an apparatus to assign locks to threads and a computer program product to assign locks to threads.

Abstract: An expansion card is provided that allows resources allocated to the expansion card to be shared with a different card. The expansion card comprises a coupling device that couples the expansion card to a data processing system. The expansion card also includes an identifier data structure that when queried by the data processing system, identifies the expansion card as a resource sharing expansion card. The data processing system reallocates one or more resources allocated to the expansion card to a different card coupled to the data processing system.

Abstract: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.

Abstract: Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions.

Abstract: Methods and computer program products for providing warnings and hints related to coding conventions using a coding style definition are provided. A source code is received, and a coding style definition is read. The source code is parsed to determine whether the source code adheres to the conventions in the coding style definition. Warnings are provided to indicate where the source code deviates from the coding style definition, if the source code fails to adhere to the conventions in the coding style definition. If the source code correctly adheres to the conventions in the coding style, hints can be provided to the compiler and linker so that they can optimize effectively using information that the compiler and linker would not normally have.

Abstract: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.

Abstract: A mechanism is provided for scheduling tasks across multiple processor units of differing capacity. In a multiple processor unit system with processor units of disparate speeds, it is advantageous to have the most processing-intensive tasks run on the processor units with the highest capacity. All tasks are initially scheduled on the lowest capacity processor units. Because processor units with higher capacity are more likely to have idle time, these higher capacity processor units may pull one or more tasks onto themselves from the same or lower capacity processor units. A processor unit will attempt to pull tasks that utilize a larger percentage of the timeslice. When a higher capacity processor unit is overloaded or near capacity, the higher capacity processor unit may push tasks to processor units with the same or lower capacity. A processor unit will attempt to push tasks that utilize a smaller percentage of the timeslice.

Abstract: In one embodiment a method is disclosed for allocating memory for a processor unit in a group of processing units. The method can include receiving a memory allocation request where the request can indicate a number of binary segments to be stored. The method can determine if the number indicates a nonstandard allocation, and locate an unallocated memory address based on a multiple of the number if the number indicates a nonstandard allocation. The method can also include locating an unallocated memory address from a pool of memory addresses, where the pool of addresses includes the integer multiples of the binary segments and excludes addresses that are two times the number of binary segments such that the address can be utilized to determine the allocation.

Abstract: A method for dynamic redundancy of processing units. The method includes defining at least one of, (i) an instruction, and (ii) a call, to idle a first processing unit. Both the instruction and the call are blocking operations that shall not return while a second processing unit and the first processing unit are paired together. The method further includes executing at least one of, (i) the defined instruction, and (ii) the call, and temporarily stopping the paired processing unit. Then, the method proceeds by synchronizing the state and enabling the redundant processor execution. Afterwards, the method includes restarting execution of both processing units together.

Abstract: A method and system for efficient coalescing of memory blocks across memory heap boundaries in multiprocessor or multithread computer system. Blocks of memory are allocated into multiple heaps for exclusive utilization by separate processors or processes. Varying memory requirements result in fragmentation and increased memory utilization over time and coalescing of memory is necessary. An identification of each memory heap which contains a preceding adjacent memory block and a succeeding adjacent memory block is maintained for all memory blocks. Thereafter, each time a memory block is freed it may be coalesced across heap boundaries with an adjacent preceding or succeeding memory block by temporarily locking access to only those memory heaps containing a free preceding or succeeding adjacent memory block.