Patents by Inventor Joel Hartmann

Joel Hartmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200115340
    Abstract: The invention relates to piperidine-based compounds of formula (I) that are used to improve UV, thermal, and thermo-oxidative stability of high performance aromatic polymers in a blend or as end-cappers of the same polymers.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Applicant: SOLVAY SPECIALTY POLYMERS USA, LLC
    Inventors: Joel POLLINO, Satchit SRINIVASAN, Henry BRADLEY, Claire HARTMANN-THOMPSON, Gregory GOSCHY
  • Patent number: 7297578
    Abstract: A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: November 20, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Philippe Coronel, Joël Hartmann
  • Publication number: 20050085024
    Abstract: A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.
    Type: Application
    Filed: September 16, 2004
    Publication date: April 21, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Philippe Coronel, Joel Hartmann
  • Patent number: 6696723
    Abstract: The invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type (16), defined by a source zone, a drain zone, a channel zone (8) and a control gate zone (6), the latter being separated from the channel zone by an insulation zone (14), said five zones being implemented in a semiconductor film formed on an insulating layer (4), said memory cell being laterally insulated by one or more insulation zones (10, 12) in contact with the insulating layer.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: February 24, 2004
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joël Hartmann, Marc Belleville
  • Publication number: 20020038882
    Abstract: The invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type (16), defined by a source zone, a drain zone, a channel zone (8) and a control gate zone (6), the latter being separated from the channel zone by an insulation zone (14), said five zones being implemented in a semiconductor film formed on an insulating layer (4), said memory cell being laterally insulated by one or more insulation zones (10, 12) in contact with the insulating layer.
    Type: Application
    Filed: July 28, 1998
    Publication date: April 4, 2002
    Inventors: JOEL HARTMANN, MARC BELLEVILLE
  • Patent number: 5696718
    Abstract: Device having an electrically erasable, non-volatile memory and its production process. In a storage area the device has at least one memory cell (12) of the floating grid type with a source (16) and a drain (18) separated by a channel region (14). According to the invention, the device also comprises means (44,38) for applying a memory cell erasing voltage to the channel region (14), independently of the memory cells of adjacent areas, as a result of a complete electrical isolation or insulation of each area. Application to the production of non-volatile memories which can be carried in satellites for replacing EPROM memories.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: December 9, 1997
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann
  • Patent number: 5679970
    Abstract: A memory including a semiconductor substrate, an array of memory cells mutually electrically insulated by side insulators, wherein each memory cell includes a gate stack consisting of a gate insulator, a floating gate and a control gate separated by an electrical insulator between the gates, said gate insulator being arranged between the floating gate and the substrate, a source and a drain formed in the substrate on either side of said stack and outside the side insulators, an erasing gate located above the source in partial overlap with the stack, and electrically insulated from the source and said stack by a thin insulator, as well as conductive strips for applying electrical signals to the gate stacks, erasing gates, sources and drains.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: October 21, 1997
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann
  • Patent number: 5336628
    Abstract: An improved integrated circuit and fabrication method for forming the improved integrated circuit is described. The method includes an anisotropic etching, without the use of either masks or photolithography, which removes insulating material from contact openings, but keeps insulating material on the sides of conductive layers, preventing inadvertent short circuits from the contact openings to the conductive layers. The maskless etching method makes it possible to avoid mask-wafer alignment errors and therefore frees designers to perfectly center contact openings within insulative regions without taking into account the surface area tolerances required under prior art fabrication methods. This freedom allows designers to design more highly integrated devices. The particular embodiments of the semiconductor integrated circuit may include floating gates (47) and control gates (52) covered with an upper oxide layer (53) on which electrical connection lines (11) have been installed.
    Type: Grant
    Filed: April 13, 1993
    Date of Patent: August 9, 1994
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann
  • Patent number: 5256584
    Abstract: Method for producing a non-volatile memory cell and obtained memory cell.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: October 26, 1993
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann
  • Patent number: 5246882
    Abstract: A method of making an electric contact of an MIS integrated circuit includes the following stages: depositing a thick film made of one first electric nonconductor on the integrated circuit provided with this element; depositing on the first nonconductor film a crash or barrier film made of a highly resistive material or a nonconductor able to be etched selectively with respect to the first nonconductor and a second electric nonconductor; forming opposite the active element a first opening in the barrier film and fixing the dimensions at the level of the active element of the electric contact to be embodied; depositing on the resulting structure obtained at least one second nonconducting film forming a second opening in the second nonconducting film, the second opening having a width larger than that the first opening; etching of the first nonconductor exposed during the previous step by using the etched barrier film as a mask, thus forming an electric contact hole of the active element, and metallizing of thi
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: September 21, 1993
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann
  • Patent number: 4682403
    Abstract: A method for interconnecting the active zones and/or gates of CMOS integrated circuits. The method comprises, during the formation of the gates in a first conductive coating, defining in the latter the dimensions of the connections to be produced, and wherein following the formation of the active zones, the gates are laterally insulated and then a second conductive coating producing the desired connections is deposited on the complete circuit, with the exception of the lateral insulation.
    Type: Grant
    Filed: March 25, 1985
    Date of Patent: July 28, 1987
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joel Hartmann, Pierre Jeuch
  • Patent number: 4672313
    Abstract: A device for checking the mobile electrical charges in a MOS integrated circuit having a wafer support, a polarization means applying a potential difference between the two faces of the silicon wafer on which are formed the integrated circuits by means of two electrodes, one constituted by a conductive diaphragm covering the silicon wafer and which is kept in contact with the silicon wafer by a pressure difference between these two faces, while the other is constituted by the electrically conductive wafer support.
    Type: Grant
    Filed: February 16, 1984
    Date of Patent: June 9, 1987
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joel Hartmann, Pierre Jeuch
  • Patent number: 4636281
    Abstract: Process for the autopositioning of a local field oxide relative to an insulating trench.This process consists of forming at least one first insulating coating on a silicon substrate, producing a second insulating coating on the first coating, anisotropically etching the first and second coating until the region of the substrate in which the trench is to be formed is exposed, forming insulating spacers on the etched flanks of the first and second coatings, anisotropically etching the substrate region in order to form the trench, the second etched coating and the spacers used as a mask for said etching, eliminating the mask, forming the insulating edges in the trench, filling said trench with a material and forming the field oxide.
    Type: Grant
    Filed: June 13, 1985
    Date of Patent: January 13, 1987
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Francois Buiguez, Joel Hartmann
  • Patent number: 4632725
    Abstract: A method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit characterized in that, after producing the constituent elements of the integrated circuit with the exception of the connections, on the complete circuit is directly deposited a coating of a conductive material, which is then etched in order to form the desired connection.
    Type: Grant
    Filed: March 15, 1985
    Date of Patent: December 30, 1986
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joel Hartmann, Pierre Jeuch
  • Patent number: 4624864
    Abstract: This process consists of depositing a first conductive coating on the complete circuit, depositing on said coating a filling material used for filling the contact hole, the surface of said material being substantially planar, carrying out an anisotropic etching of said filling material so as to expose those parts of the first conductive coating located outside the contact hole and only retaining that part of said filling material which fills the contact hole, depositing on the structure obtained a second conductive coating in which the interconnection line will be formed, producing in the second conductive coating a resin mask used for defining the dimensions of the line, eliminating those parts of the second and first conductive coatings which are free from the mask and eliminating the mask.
    Type: Grant
    Filed: June 13, 1985
    Date of Patent: November 25, 1986
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Joel Hartmann