Patents by Inventor Joel Hatsch
Joel Hatsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230244820Abstract: A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line.Type: ApplicationFiled: January 12, 2023Publication date: August 3, 2023Inventors: Stefan Seidl, Joel Hatsch, Artur Wroblewski
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Publication number: 20230153472Abstract: A bit generation circuit having a plurality of signal chains, where for each chain, a first input of an input multiplexer is connected to another of the signal chains and the multiplexer is configured so that, if a control signal indicating a normal operating mode is fed to the multiplexer, the multiplexer connects the first input to the path input of the signal chain. The second input of each multiplexer is connected to the output of a bit generation trigger circuit and, for each signal chain, the multiplexer is configured so that, if a control signal indicating a secret generation mode is fed to the multiplexer, it connects the second input to the path input of the signal chain. The bit generation circuit furthermore comprises an arbiter circuit connected to the path outputs of at least two signal chains and configured to output a secret bit depending on their states.Type: ApplicationFiled: November 9, 2022Publication date: May 18, 2023Inventors: Stefan Seidl, Joel Hatsch, Artur Wroblewski
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Publication number: 20220293852Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.Type: ApplicationFiled: March 8, 2022Publication date: September 15, 2022Inventors: Artur Wroblewski, Joel Hatsch, Christoph Saas, Stefan Seidl
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Patent number: 10628084Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.Type: GrantFiled: October 10, 2018Date of Patent: April 21, 2020Assignee: Infineon Technologies AGInventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
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Patent number: 10276222Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.Type: GrantFiled: May 13, 2015Date of Patent: April 30, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Thomas Kuenemund, Gerd Dirscherl, Gunther Fenzl, Joel Hatsch, Nikolai Sefzik
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Publication number: 20190114111Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.Type: ApplicationFiled: October 10, 2018Publication date: April 18, 2019Inventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
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Publication number: 20150332756Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.Type: ApplicationFiled: May 13, 2015Publication date: November 19, 2015Inventors: Thomas KUENEMUND, Gerd DIRSCHERL, Gunther FENZL, Joel HATSCH, Nikolai SEFZIK
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Patent number: 8854866Abstract: A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.Type: GrantFiled: June 17, 2011Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Peter Huber, Winfried Kamp, Joel Hatsch, Michel d'Argouges, Siegmar Koeppe, Thomas Kuenemund
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Patent number: 8605526Abstract: Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present discloser relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.Type: GrantFiled: May 31, 2011Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Peter Huber, Joel Hatsch, Karl Hofmann, Siegmar Koeppe
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Publication number: 20120307579Abstract: Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Infineon Technologies AGInventors: Peter Huber, Joel Hatsch, Karl Hofmann, Siegmar Koeppe
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Publication number: 20120020145Abstract: A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.Type: ApplicationFiled: June 17, 2011Publication date: January 26, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Huber, Winfried Kamp, Joel Hatsch, Michel d'Argouges, Siegmar Koeppe
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Patent number: 7716270Abstract: A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.Type: GrantFiled: March 13, 2006Date of Patent: May 11, 2010Assignee: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp
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Patent number: 7487198Abstract: The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.Type: GrantFiled: October 8, 2004Date of Patent: February 3, 2009Assignee: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp
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Publication number: 20060294178Abstract: A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.Type: ApplicationFiled: August 12, 2005Publication date: December 28, 2006Inventors: Marc Bernhardt, Joel Hatsch, Winfried Kamp, Siegmar Koeppe
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Publication number: 20060235923Abstract: A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2 w.Type: ApplicationFiled: March 13, 2006Publication date: October 19, 2006Inventors: Joel Hatsch, Winfried Kamp
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Patent number: 6977831Abstract: One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.Type: GrantFiled: September 17, 2004Date of Patent: December 20, 2005Assignee: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp, Thomas Künemund, Holger Sedlak, Heinz Söldner
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Patent number: 6978290Abstract: A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.Type: GrantFiled: April 5, 2002Date of Patent: December 20, 2005Assignee: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp, Siegmar Köppe, Ronald Künemund, Eva Lackerschmid, Heinz Söldner
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Publication number: 20050114424Abstract: The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.Type: ApplicationFiled: October 8, 2004Publication date: May 26, 2005Applicant: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp
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Publication number: 20050094477Abstract: One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.Type: ApplicationFiled: September 17, 2004Publication date: May 5, 2005Inventors: Joel Hatsch, Winfried Kamp, Thomas Kunemund, Holger Sedlak, Heinz Soldner
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Publication number: 20040159712Abstract: A carry-save adder for adding bits of the same weight comprises six inputs (I0, I1, . . . , I5) for receiving six bits of in each case the same weight w, to be added. The adder has an output (S) for a sum bit of weight w and two outputs (C0, C1) for two carry bits of weights 2w and 4w.Type: ApplicationFiled: December 15, 2003Publication date: August 19, 2004Inventors: Joel Hatsch, Winfried Kamp, Siegmar Koppe, Ronald Kunemund, Eva Lackerschmid, Heinz Soldner