Abstract: Certain aspects of the present disclosure provide techniques and apparatus for improved machine learning. Voice data from a first user is received. In response to determining that the voice data includes an utterance of a defined keyword, a user verification score is generated by processing the voice data using a first user verification machine learning (ML) model, and a quality of the voice data is determined. In response to determining that the user verification score and determined quality satisfy one or more defined criteria, a second user verification ML model is updated based on the voice data.

Abstract: The application is directed to methods and devices for estimating corrosion of a material. One of the methods includes obtaining data regarding corrosion. The data is obtained from various sources, such as but not limited to sensors and observational data. The data is then trained to provide for a more complete data set. The trained data is then used to estimate the expected amount of corrosion for a given situation.

Abstract: A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is generated therefrom, for example, by referencing a lookup table. The microcode event handler vector is then used for invoking a microcode event handler to handle occurrence of these events in the processor. By the formation of an event vector, and the microcode event handler vector, execution performance is increased due to avoiding conditional branching within the processor, such as modem high performance architectures, including those which execute instructions in and out-of-order.

Abstract: A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a pre-determined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state.

Abstract: A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.

Abstract: A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a predetermined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state.

Abstract: A voltage regulator circuit includes a variable resistance formed by diode configuration of NMOS depletion transistors connected in a parallel relation with a supply voltage divider connected at a node by a further variable resistance formed by a serial arrangement of NMOS transistors with ground and having each of their gates coupled to the supply voltage.