Abstract: An anti-theft device for securing an article of merchandise against unauthorized removal from a display counter. The anti-theft device comprises a latch plate and a pedestal having a quick-release interface. The latch plate is configured to selectively couple to the quick-release interface. A latch bolt is disposed within the pedestal. The latch bolt locks the latch plate relative to the quick-release interface. A plurality of retaining arms is configured to receive and retain an article of merchandise. The retaining arms cannot be disengaged from the article of merchandise while the latch plate is locked relative to the quick-release interface. A solenoid is housed within the pedestal and operationally connected to the latch bolt. The solenoid is configured to retract the latch bolt into a position in which the latch bolt disengages the latch plate, thereby releasing the latch plate from the quick-release interface.

Abstract: A security device for a retail item or packaging has housing that retains a gear that is operably connected to a pawl with two arms. One arm of the pawl is operably engaged by the gear. The other arm of the pawl is operably engaged with an unlocking key within the housing. The unlocking key is operably controlled by an unlocking tool by inserting a portion of the unlocking tool into a complementary portion of the unlocking key through a keyway formed in the housing. The unlocking key may have a magnet or components that are attracted to a magnet that enable the unlocking key to disengage a slot formed in the housing to allow the unlocking key to rotate to move the pawl. The housing may additionally be formed with a channel that allows a plurality of similarly constructed security devices to be tethered or daisy-chained together.

Abstract: A high capacity nut grinder includes an auger configured to slice nuts as they are received from a hopper and convey the nuts from the hopper to a receiving volume between a pair of grinding plates. Optionally, the nut grinder can include a sleeve including an asymmetrical aperture configured to cooperate with the nut auger to slice nuts without expelling nuts upward into the nut hopper.

Abstract: A nut grinder includes a nut auger, a stationary grinding plate, and a rotatable grinding plate configured to grind nuts. The nut auger and rotatable grinding plate may be adapted to receive rotational power from a human user or a mechanical source.

Abstract: A nut grinder includes a nut auger, a stationary grinding plate, and a rotatable grinding plate configured to grind nuts. The nut auger and rotatable grinding plate may be adapted to receive rotational power from a human user or a mechanical source.

Abstract: A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

Abstract: A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1.

Abstract: A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1.

Abstract: A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

Abstract: A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.

Abstract: The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.