Abstract: A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: The method for efficiently providing an optimized fanout network includes the steps of providing a series chain of inverters for driving a number of loads. Each load is assigned to a given location of the inverter chain according to the polarity and the required time of the load. Tree-covering techniques are used in conjunction with dynamic programming to minimize the total area of the fanout chain by selecting and sizing the gates to be used in the fanout chain. With such an arrangement, a minimal area fanout chain which satisfies the timing constraints of each load is provided.